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参数资料
型号： STM8L151R6T3DSTM8L151R6T3D
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64
封装： 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件页数： 105/122页
文件大小： 1190K
代理商： STM8L151R6T3DSTM8L151R6T3D
STM8L15xx8, STM8L15xR6
Electrical parameters
Doc ID 17943 Rev 1
83/122
9.3.4
Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
4.
Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.
5.
Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
6.
Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
7.
Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD /2. Floating DAC output.
8.
Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
9.
Including supply current of internal reference voltage.
Table 27.
Current consumption under external reset
Symbol
Parameter
Conditions
Typ
Unit
IDD(RST)
Supply current under
external reset (1)
PB1/PB3/PA5 pins are
externally tied to VDD
VDD = 1.8 V
48
A
VDD = 3 V
80
VDD = 3.6 V
95
1.
All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.
Table 28.
HSE external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHSE_ext
External clock source
frequency(1)
1.
Guaranteed by design, not tested in production.
116
MHz
VHSEH
(2)
2.
Data based on characterization results, not tested in production.
OSC_IN input pin high level
voltage
0.7 x VDD
VDD
V
VHSEL
(2)
OSC_IN input pin low level
voltage
VSS
0.3 x VDD
Cin(HSE)
OSC_IN input
capacitance(1)
2.6
pF
ILEAK_HSE
OSC_IN input leakage
current
VSS < VIN < VDD
±1
A
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