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| 型号： | STP2013PGA-50 |
| 元件分类： | 参考电压二极管 |
| 英文描述： | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| 中文描述： | 250 的低电流运算，低反向泄露，低噪声稳压二极管 |
| 文件页数： | 4/20页 |
| 文件大小： | 221K |
| 代理商： | STP2013PGA-50 |
4
STP2000QFP
32-bit SBus Master I/O Controller
Master I/O
July 1997
S
IGNAL
D
ESCRIPTIONS
1. The CHIP_SEL pin is an additional qualifier (active high) to the SB_SEL line. In some system configurations where the STP2000
(Master I/O Controller) and the STP2001 (Slave I/O Controller) share a single SBus select line, PA[27] can be used to select
between the two.
SBus Interface
Name
Type
Description
SB_D[31:0]
I/O
SBus Data Bus (MSB)
SB_BR
I/O
SBus Bus Request
SB_BG
Input
SBus Bus Grant
SB_ACK[2:0]
I/O
SBus Acknowledge
SB_RESET
Input
SBus Reset
SB_LERR
Input
SBus Late Error (INT15)
SB_CLK
Input
SBus Clock Input
SB_RD
I/O
SBus Read/Write
SB_SEL
Input
SBus Select
SB_D_IRQ
Output
SBus Interrupt for SCSI transfers (open-drain)
SB_E_IRQ
Output
SBus Interrupt for ETHERNET transfers (open-drain)
SB_P_IRQ
Output
SBus Interrupt for Parallel Port Transfers (open-drain)
SB_SIZ[2:0]
I/O
SBus Transfer Size
SB_AS
CHIP_SEL
[1]
Input
SBus Address Strobe (address is valid)
Input
High order physical address bit
SB_PA[W]
Input
High order physical address bit
SB_PA[X]
Input
High order physical address bit
SB_PA[Y]
Input
High order physical address bit
SB_PA[5:0]
Input
Low order physical address bits
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