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参数资料
| 型号： | STP2223BGA |
| 元件分类： | 总线控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 15/34页 |
| 文件大小： | 476K |
| 代理商： | STP2223BGA |
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22
STP2223BGA
UPA to PCI Interface
U2P
July 1997
(1) PCIA VDD5 - For proper noise immunity, tie to 3.3V for PCI cards which use 3V signalling, tie to 5V for PCI cards which use 5V signalling.
(2) MISC VDD5 - Tie to 5V. Internal to U2P these three pins are part of a single voltage rail.
(3) A_CLK, B_CLK - used by U2P to determine the clock phase of a given PCIA, PCIB cycle, respectively. Required since either bus can be running
at half the frequency of the internal clock.
Input Buffers
U2P implements four types of input buffers:
1. TTL
UPA and JTAG inputs
2. 5V tolerant TTL
INT_NUM and TMR_CLK inputs
3. PCI
PCI inputs (5V tolerant)
4. PECL
UPA_CLK and UPA_CLK_L inputs
Note:
Refer to the Lucent Technologies HL350C 3 Volt 0.35 micron. CMOS Standard-Cell Library data
book for full specification on the buffer types. Generally an input buffer is 5 Volt tolerant if it is a
PCI buffer (and VDD5 is tied to 5 Volts) or if it is of type B5xxxx.
B_AD[8]
AF13
IO
PCI21LUS
PCIB address/data bus
B_AD[3]
AF14
IO
PCI21LUS
PCIB address/data bus
B_CBE_[7]
AF15
IO
PCI21LUS
PCIB command/byte enable bus
VSS
AF16
VDD
AF17
B_TRDY_
AF18
IO
PCI21LUS
PCIB target ready
B_PERR_
AF19
IO
PCI21LUS
PCIB bus parity error
B_GNT_[3]
AF20
O
PCI21LUS
PCIB bus grant
VSS
AF21
VDD
AF22
B_CLK
AF23
I
PCI21LIS
PCIB bus clock phase detect (note 3)
A_REQ_[3]
AF24
I
PCI21MIN
PCIA bus request
VSS
AF25
VDD
AF26
TABLE 3: PBGA Pinout (Continued)
Signal Name
Ball
Direction
Cell Type
Description
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