参数资料
型号: STR712FZH1TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PBGA144
封装: 10 X 10 MM, 1.70 MM HEIGHT, LFBGA-144
文件页数: 60/78页
文件大小: 2018K
代理商: STR712FZH1TR
STR71xF
Electrical parameters
63/78
4.3.9
BSPI - buffered serial peripheral interface
Subject to general operating conditions for VDD, TA and fPCLK1 ,unless otherwise specified.
Refer to I/O port pin characteristics on page 50 for more details on the input/output alternate
function characteristics (SS, SCK, MOSI, MISO).
Table 38.
BSPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master
fPCLK1/254
fPCLK1/6
5.5
MHz
Slave
0
fPCLK1/8
3.3
tr(SCK)
tf(SCK)
SPI clock rise and fall time
capacitive charge
C=50 pF
14
ns
tsu(SS)
(1)
SS setup time
Slave
0
th(SS)
SS hold time
Slave
0
tw(SCKH)
tw(SCKL)
SCK high and low time
Master fPCLK1=33 MHz,
presc = 6
73
tsu(MI)
tsu(SI)
Data input setup time
Master
Slave
7
0
th(MI)
1)(2)
th(SI)
Data input hold time
Master
Slave
1xtPCLK1
2xtPCLK1
th(MI)
th(SI)
Data input hold time
Master fPCLK1=33 MHz
Slave fPCLK1=33 MHz
30
60
ta(SO)
1)(3)
Data output access time
Slave
0
1.5xtPCLK1+42
Slave fPCLK1=33 MHz
0
87
tdis(SO)
(1)(4)
Data output disable time
Slave
0
42
tv(SO)
Data output valid time
Slave (after enable edge)
3xtPCLK1+45
fPCLK1=33 MHz
135
th(SO)
Data output hold time
Slave (after enable edge)
0
tv(MO)
Data output valid time
Master (after enable edge)
2xtPCLK1+12
fPCLK1=33 MHz
72
th(MO)
Data output hold time
Master (after enable edge)
0
1.
Data based on design simulation and/or characterisation results, not tested in production.
2.
Depends on fPCLK1. For example, if fPCLK1=8 MHz, then tPCLK1 = 1/fPCLK1 =125 ns and tv(MO) = 255 ns.
3.
Min. time is the minimum time to drive the output and the max. time is the maximum time to validate the data.
4.
Min time is the minimun time to invalidate the output and the max time is the maximum time to put the data in Hi-Z.
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