参数资料
型号: STR912FAZ42H6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 96 MHz, RISC MICROCONTROLLER, PBGA144
封装: 10 X 10 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-144
文件页数: 15/101页
文件大小: 1922K
代理商: STR912FAZ42H6
Functional overview
STR91xFAxxx
3.10
Clock control unit (CCU)
The CCU generates a master clock of frequency fMSTR. From this master clock the CCU
also generates individually scaled and gated clock sources to each of the following
functional blocks within the STR91xFA.
CPU, fCPUCLK
Advanced High-performance Bus (AHB), fHCLK
Advanced Peripheral Bus (APB), fPCLK
Flash Memory Interface (FMI), fFMICLK
External Memory Interface (EMI), fBCLK
UART Baud Rate Generators, fBAUD
USB, fUSB
3.10.1
Master clock sources
The master clock in the CCU (fMSTR) is derived from one of three clock input sources. Under
firmware control, the CPU can switch between the three CCU inputs without introducing any
glitches on the master clock output. Inputs to the CCU are:
Main Oscillator (fOSC). The source for the main oscillator input is a 4 to 25 MHz external
crystal connected to STR91xFA pins X1_CPU and X2_CPU, or an external oscillator
device connected to pin X1_CPU.
PLL (fPLL). The PLL takes the 4 to 25 MHz oscillator clock as input and generates a
master clock output up to 96 MHz (programmable). By default, at power-up the master
clock is sourced from the main oscillator until the PLL is ready (locked) and then the
CPU may switch to the PLL source under firmware control. The CPU can switch back to
the main oscillator source at any time and turn off the PLL for low-power operation. The
PLL is always turned off in Sleep mode.
RTC (fRTC). A 32.768 kHz external crystal can be connected to pins X1_RTC and
X2_RTC, or an external oscillator connected to pin X1_RTC to constantly run the real-
time clock unit. This 32.768 kHz clock source can also be used as an input to the CCU
to run the CPU in slow clock mode for reduced power.
As an option, there are a number of peripherals that do not have to receive a clock sourced
from the CCU. The USB interface can receive an external clock on pin P2.7, TIM timers
TIM0/ TIM1 can receive an external clock on pin P2.4, and timers TIM2/TIM3 on pin P2.5.
29
VIC1.13
Wake-up Group 3
Logic OR of 8 interrupts from pins P7.0 to P7.7
30
VIC1.14
USB
USB Bus Resume Wake-up (also input to wake-up unit)
31 (low priority)
VIC1.15
PFQ-BC
Special use of interrupts from Prefetch Queue and Branch Cache
Table 6.
VIC IRQ Channels (continued)
IRQ Channel
hardware
priority
VIC input
channel
Logic Block
Interrupt Source
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