Programmable logic device (PLD) manufactured using a 0.15-μm alllayer copper-metal fabrication process (up to eight layers of metal) – 1-gigabit per second (Gbps) True-LVDS TM , LVPECL, pseudo current mode logic (PCML), and HyperTransport TM interface – Clock-data synchronization (CDS) in True-LVDS interface to correct any fixed clock-to-data skew – Enables common networking and communications bus I/O standards such as RapidIOTM , CSIX, Utopia IV, and POS-PHY Level 4 – Support for high-speed external memory interfaces, including zero bus turnaround (ZBT), quad data rate (QDR), and double data rate (DDR) static RAM (SRAM), and single data rate (SDR) and DDR synchronous dynamic RAM (SDRAM) – 30% to 40% faster design performance than APEXTM 20KE devices on average – Enhanced 4,096-bit embedded system BLOCKs (ESBs) implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM (bidirectional dual-port RAM), and content-addressable memory (CAM) – High-performance, low-power copper interconnect – Fast parallel byte-wide synchronous device configuration – Look-up table (LUT) logic available for register-intensive functions ■ High-density architecture – 1,900,000 to 5,250,000 maximum system gates (see Table 1) – Up to 67,200 logic elements (LEs) – Up to 1,146,880 RAM bits that can be used without reducing available logic ■ Low-power operation design – 1.5-V supply voltage – Copper interconnect reduces power consumption – MultiVolt TM I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces – ESBs offer programmable power-saving mode

I/O features – Up to 380 Gbps of I/O capability – 1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport support on 36 input and 36 output channels that feature clock synchronization circuitry and independent clock multiplication and serialization/deserialization factors – Common networking and communications bus I/O standards such as RapidIO, CSIX, Utopia IV, and POS-PHY Level 4 enabLED – 400-megabits per second (Mbps) Flexible-LVDS and HyperTransport support on up to 88 input and 88 output channels (input channels also support LVPECL) – Support for high-speed external memories, including ZBT, QDR, and DDR SRAM, and SDR and DDR SDRAM – Compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits – Compliant with 133-MHz PCI-X specifications – Support for other advanced I/O standards, including AGP, CTT, SSTL-3 and SSTL-2 Class I and II, GTL+, and HSTL Class I and II – Six dedicated registers in each I/O element (IOE): two input registers, two output registers, and two output-enable registers – Programmable bus hold feature – Programmable pull-up resistor on I/O pins available during user mode

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