参数资料
型号: SX1230I066TRT
厂商: Semtech
文件页数: 13/46页
文件大小: 0K
描述: IC TX UHF 433/868/916 MHZ 24-QFN
特色产品: SX1230 Integrated Transmitter IC
标准包装: 1
频率: 315MHz,434MHz,868MHz,915MHz
应用: RKE
调制或协议: ISM
数据传输率 - 最大: 600kbps
功率 - 输出: 17dBm
电流 - 传输: 95mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 1.8 V ~ 3.7 V
工作温度: -40°C ~ 85°C
封装/外壳: 24-MLPQ
包装: 标准包装
产品目录页面: 584 (CN2011-ZH PDF)
其它名称: SX1230I066DKR
SX1230
Integrated Transmitter IC
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
Table 7
Example Standard Bitrates and their Corresponding Register Settings.
Type
Classical modem baud rates
(multiples of 1.2 kbps)
Classical modem baud rates
(multiples of 0.9 kbps)
Round bit rates
(multiples of 12.5, 25 and
50 kbps)
Watch Xtal frequency
BrMSB
0x68
0x34
0x1A
0x0D
0x06
0x03
0x01
0x00
0x02
0x01
0x0A
0x05
0x80
0x01
0x00
0x00
0x00
0x00
0x03
BrLSB
0x2B
0x15
0x0B
0x05
0x83
0x41
0xA1
0xD0
0x2C
0x16
0x00
0x00
0x00
0x40
0xD5
0xA0
0x80
0x6B
0xD1
(G)FSK, (G)MSK
1.2 kbps
2.4 kbps
4.8 kbps
9.6 kbps
19.2 kbps
38.4 kbps
76.8 kbps
153.6 kbps
57.6 kbps
115.2 kbps
12.5 kbps
25 kbps
50 kbps
100 kbps
150 kbps
200 kbps
250 kbps
300 kbps
32.768 kbps
OOK
1.2 kbps
2.4 kbps
4.8 kbps
9.6 kbps
19.2 kbps
12.5 kbps
25 kbps
32.768 kbps
Rb Actual (to 7s.f.)
1200.015
2400.060
4799.760
9600.960
19196.16
38415.36
76738.60
153846.1
57553.95
115107.9
12500.00
25000.00
50000.00
100000.0
150234.7
200000.0
250000.0
299065.4
32753.32
5.2. Synthesizer
The frequency synthesizer of the SX1230 is a fully integrated fractional-N third-order sigma-delta phase-locked loop and
VCO. Also incorporated are fully integrated third-order and low pass filters which determine the loop bandwidth. All of these
features are fully automated and derived from the user bitrate and frequency deviation settings, as described in Sections
5.1.1 to 5.1.3.
To ensure the frequency accuracy of the PLL output it is necessary to perform calibration. The calibration process is
performed automatically upon power up of the SX1230. However, the calibration feature is also accessible to the user via
the SPI configuration register, PllStat (address 0x0A). The calibration is performed by setting bit 2 (pll_cal) high. This
ensures that the frequency output accuracy is limited only by the frequency error of the crystal oscillator, the calibration
procedure lasts 500 μs, during which time pll_cal_done (bit 4 of address 0x0A) is set low. Once complete pll_cal_done is
set high and confirmation of a successful calibration can be obtained by reading pll_cal_ok.
SX1230, Revision 2 May 2009
?2008 Semtech Corp.
Page 13
www.semtech.com
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