参数资料
| 型号： | SY100E155JC |
| 厂商： | Micrel Inc |
| 文件页数： | 1/4页 |
| 文件大小： | 0K |
| 描述： | IC MUX-LATCH 6-BIT 2:1 28-PLCC |
| 标准包装： | 38 |
| 系列： | 100E |
| 类型： | 多路复用器 |
| 电路： | 6 x 2:1 |
| 独立电路： | 1 |
| 电压电源： | 单电源 |
| 电源电压： | 4.2 V ~ 5.5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC |
| 包装： | 管件 |
750ps max. LEN to output
Extended 100E VEE range of –4.2V to –5.5V
700ps max. D to output
Single-ended outputs
Asynchronous Master Reset
Dual latch-enables
Fully compatible with industry standard 10KH,
100K ECL levels
Internal 75K input pulldown resistors
Fully compatible with Motorola MC10E/100E155
Available in 28-pin PLCC package
FEATURES
The SY10/100E155 offer six 2:1 multiplexers followed
by latches with single-ended outputs, designed for use in
new, high-performance ECL systems. The two external
latch-enable signals (LEN1 and LEN2) are gated through a
logical OR operation before use as control for the six
latches. When both LEN1 and LEN2 are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN1 or LEN2 (or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL (Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
DESCRIPTION
Rev.: C
Amendment: /1
Issue Date: February, 1998
6-BIT 2:1
MUX-LATCH
SY10E155
SY100E155
FINAL
BLOCK DIAGRAM
PIN CONFIGURATION
PIN NAMES
n
o
it
c
n
u
F
n
i
P
D0a–D5a
Input Data a
D0b–D5b
Input Data b
t
u
p
n
I
t
c
e
l
e
S
a
t
a
D
L
E
S
LEN1, LEN2
Latch Enables
t
e
s
e
R
r
e
t
s
a
M
R
M
Q0–Q5
Outputs
VCCO
VCC to Output
VEE
D5b
LEN1
SEL
MR
NC
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5678
9 10 11
D0b
LEN2
Q
0
V
CCO
Q5
D
3a
PLCC
TOP VIEW
J28-1
D
5a
D
3b
D
4a
Q4
VCC
Q3
Q2
VCCO
Q1
D
2b
D
2a
D
1b
D
1a
D
0b
D
4b
V
CCO
D
R
Q
MUX
SEL
D
R
Q
MUX
D
R
Q
MUX
D
R
Q
MUX
D
R
Q
MUX
D
R
Q0
Q1
Q2
Q3
Q4
Q5
Q
MUX
MR
D0a
LEN1
LEN2
SEL
D0b
D1a
D1b
D2a
D2b
D3a
D3b
D4a
D4b
D5a
D5b
E
N
E
N
E
N
E
N
E
N
E
N
SEL
1
REV: D
Issue Date: September 2011
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY100E155JCTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:6-BIT 2:1 MUX-LATCH |
| SY100E155JZ | 功能描述:编码器、解码器、复用器和解复用器 6-bit 2:1 Mux-Latch (Lead Free) RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| SY100E155JZ TR | 功能描述:编码器、解码器、复用器和解复用器 6-bit 2:1 Mux-Latch (Lead Free) RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
| SY100E156 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3-BIT 4:1 MUX-LATCH |
| SY100E156JC | 功能描述:IC MUX-LATCH 3-BIT 4:1 28-PLCC RoHS:否 类别:集成电路 (IC) >> 逻辑 - 信号开关，多路复用器，解码器 系列:100E 标准包装:25 系列:74HC 类型:解码器 电路:1 x 2:4 独立电路:2 输出电流高，低:5.2mA，5.2mA 电压电源:单电源 电源电压:2 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-DIP 包装:管件 |
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