参数资料
| 型号： | SY100E195JI |
| 厂商： | Micrel Inc |
| 文件页数： | 1/8页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 128TAP 28-PLCC |
| 标准包装： | 38 |
| 系列： | 100E, Precision Edge® |
| 标片/步级数： | 128 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 1.39ns |
| 接头增量： | 20ps |
| 可用的总延迟： | 1.39ns ~ 3.63ns |
| 独立延迟数： | 1 |
| 电源电压： | -4.2 V ~ -5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC |
| 包装： | 管件 |
1
Precison Edge
SY10E195
SY100E195
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
IN/IN
Signal Input
EN
Input Enable
D[0:7]
Mux Select Inputs
Q/Q
Signal Output
LEN
Latch Enable
SET MIN
Minimum Delay Set
SET MAX
Maximum Delay Set
CASCADE
Cascade Signal
DESCRIPTION
FEATURES
PIN NAMES
PROGRAMMABLE
DELAY CHIP
Precison Edge
SY10E195
SY100E195
s Up to 2ns delay range
s Extended 100E VEE range of –4.2V to –5.5V
s
≈20ps/digital step resolution
s >1GHz bandwidth
s On-chip cascade circuitry
s 75Kk
input pulldown resistor
s Fully compatible with Motorola MC10E/100E195
s Available in 28-pin PLCC package
The SY10/100E195 are programmable delay chips
(PDCs) designed primarily for clock de-skewing and timing
adjustment. They provide variable delay of a differential
ECL input transition.
The delay section consists of a chain of gates
organized as shown in the logic diagram. The first two
delay elements feature gates that have been modified to
have delays 1.25 and 1.5 times the basic gate delay of
approximately 80ps. These two elements provide the
E195
with
a
digitally-selectable
resolution
of
approximately 20ps. The required device delay is selected
by the seven address inputs D[0:6], which are latched
on-chip by a high signal on the latch enable (LEN) control.
If the LEN signal is either LOW or left floating, then the
latch is transparent.
Because the delay programmability of the E195 is
achieved by purely differential ECL gate delays, the
device will operate at frequencies of >1GHz, while
maintaining over 600mV of output swing.
The E195 thus offers very fine resolution, at very high
frequencies, selectable entirely from a digital input,
allowing for very accurate system clock timing.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
Rev.: H
Amendment: /0
Issue Date:
March 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY100E195JI TR | 功能描述:IC DELAY LINE 128TAP 28-PLCC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:100E, Precision Edge® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| SY100E195JITR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP |
| SY100E195JY | 功能描述:IC DELAY LINE 128TAP 28-PLCC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:100E, Precision Edge® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| SY100E195JY TR | 功能描述:IC DELAY LINE 128TAP 28-PLCC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:100E, Precision Edge® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| SY100E195JYTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP |
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