参数资料
| 型号： | SY100E196JI |
| 厂商： | Micrel Inc |
| 文件页数： | 1/10页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 7TAP 28-PLCC |
| 标准包装： | 38 |
| 系列： | 100E, Precision Edge® |
| 标片/步级数： | 7 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 1.39ns |
| 接头增量： | 20ps |
| 可用的总延迟： | 1.39ns ~ 3.63ns |
| 独立延迟数： | 1 |
| 电源电压： | -4.2 V ~ -5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC |
| 包装： | 管件 |
1
Precision Edge
SY10E196
SY100E196
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
FEATURES
PROGRAMMABLE DELAY
CHIP WITH ANALOG INPUT
Precision Edge
SY10E196
SY100E196
s Up to 2ns delay range
s Extended 100E VEE range of –4.2V to –5.5V
s
≈20ps digital step resolution
s Linear input for tighter resolution
s >1GHz bandwidth
s On-chip cascade circuitry
s 75Kk
input pulldown resistor
s Fully compatible with Motorola MC10E/100E196
s Available in 28-pin PLCC package
The SY10/100E196 are programmable delay chips
(PDCs) designed primarily for very accurate differential
ECL input edge placement applications.
The delay section consists of a chain of gates and a
linear ramp delay adjustment organized as shown in the
logic diagram. The first two delay elements feature gates
that have been modified to have delays 1.25 and 1.5
times the basic gate delay of approximately 80ps. These
two elements provide the E196 with a digitally-selectable
resolution of approximately 20ps. The required device
delay is selected by the seven address inputs D[0:6],
which are latched on-chip by a high signal on the latch
enable (LEN) control. If the LEN signal is either LOW or
left floating, then the latch is transparent.
The FTUNE input takes an analog coltage and applies
it to an internal linear ramp for reducing the 20s resolution
still further. The FTUNE input is what differentiates the
E196 from the E195.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
Pin
Function
IN/IN
Signal Input
EN
Input Enable
D[0:7]
Mux Select Inputs
Q/Q
Signal Output
LEN
Latch Enable
SET MIN
Minimum Delay Set
SET MAX
Maximum Delay Set
CASCADE
Cascade Signal
FTUNE
Linear Voltage Input
VCCO
VCC to Output
PIN NAMES
Rev.: H
Amendment: /0
Issue Date:
March 2006
相关PDF资料 |
PDF描述 |
|---|---|
| ISL95811UFUZ-TK | IC POT 256TAPS 5BYTES 8-MSOP |
| MS3452W20-21SW | CONN RCPT 9POS BOX MNT W/SCKT |
| M83723/72W22198 | CONN RCPT 19POS WALL MT W/PINS |
| SY100EP196VTI | IC DELAY LINE 1024TAP 32-TQFP |
| MS3101A36-15SW | CONN RCPT 35POS FREE HNG W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SY100E196JITR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E196JY | 功能描述:延迟线/计时元素 Programmable Delay Chip (I Temp, Lead Free) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| SY100E196JYTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E212 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3-BIT SCANNABLE REGISTER |
| SY100E212JC | 功能描述:IC REGISTER 3-BIT SCAN 28-PLCC RoHS:否 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:100E 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。