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参数资料
| 型号： | SY100EL14VZYTR |
| 厂商： | MICREL INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 100EL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 0.300 INCH, LEAD FREE, SOIC-20 |
| 文件页数： | 1/4页 |
| 文件大小： | 56K |
| 代理商： | SY100EL14VZYTR |
The SY100EL14V is a low skew 1:5 clock distribution
chip designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. The EL14V is
suitable for operation in systems operating from 3.3V to
5.0V supplies. If a single-ended input is to be used the
VBB output should be connected to the CLK input and
bypassed to ground via a 0.01
F capacitor. The VBB
output is designed to act as the switching reference for
the input of the EL14V under single-ended input
conditions, as a result this pin can only source/sink up to
0.5mA of current.
The EL14V features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to VEE and CLK input will bias around
VCC/2.
Pin
Function
CLK
Differential Clock Inputs
SCLK
Scan Clock Input
EN
Synchronous Enable
SEL
Clock Select Input
VBB
Reference Output
Q0-4
Differential Clock Outputs
TRUTH TABLE
PIN NAMES
FEATURES
DESCRIPTION
PIN CONFIGURATION/BLOCK DIAGRAM
Precision Edge
SY100EL14V
CLK
SCLK
SEL
EN
Q
L
X
LLL
HX
L
H
XL
H
L
XH
H
L
H
XX
X
H
L*
* On next negative transition of CLK or SCLK
1
Q0
Q1
Q2
Q3
Q4
20
VCC EN VCC NC SCLK CLK CLK VBB SEL VEE
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
10
D
Q
SOIC
TOP VIEW
s 3.3V and 5V power supply options
s Typical 30ps output-to-output skew
s Max. 50ps output-to-output skew
s Synchronous enable/disable
s Multiplexed clock input
s 75K
internal input pull-down resistors
s Available in 20-pin SOIC package
5V/3.3V 1:5 CLOCK
DISTRIBUTION
1
Rev.: C
Amendment: /0
Issue Date: September 2004
Precision Edge is a trademark of Micrel, Inc.
Precision Edge
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| SY100EL15LZI | 100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY100EL15 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:1:4 CLOCK DISTRIBUTION |
| SY100EL15L | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V 1:4 CLOCK DISTRIBUTION |
| SY100EL15L_06 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V 1:4 CLOCK DISTRIBUTION |
| SY100EL15LZC | 功能描述:IC CLOCK BUFFER MUX 2:4 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:100EL, Precision Edge® 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
| SY100EL15LZC TR | 功能描述:IC CLOCK BUFFER MUX 2:4 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:100EL, Precision Edge® 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
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