参数资料
| 型号： | SY100EL17VZI |
| 厂商： | Micrel Inc |
| 文件页数： | 4/5页 |
| 文件大小： | 0K |
| 描述： | IC RCVR QUAD DIFF 5V/3.3V 20SOIC |
| 标准包装： | 38 |
| 系列： | 100EL |
| 逻辑类型： | 差分接收器 |
| 电源电压： | 3.3V，5V |
| 位数： | 8 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC（宽型） |
| 包装： | 管件 |
Micrel, Inc.
SY89218U
August 2007
4
M9999-082407-C
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
1, 2
3, 4
15, 16
17, 18
FSELA1, FSELA0
FSELB1, FSELB0
FSELC1, FSELC0
FSELD1, FSELD0
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the
four banks of outputs. Note that each of these inputs is internally connected to a 25k
pull-up resistor and will default to a logic HIGH state if left open. The input-switching
threshold is VCC/2.
5, 8,
11, 14
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the device.
These inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs
internally terminate to a VT pin through 50
. Note that these inputs will default to an
indeterminate state if left open. Please refer to the “Input Interface Applications”
section for more details.
6, 12
VT0, VT1
Input Termination Center-Tap: Each side of a differential input pair terminates to a VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “ Input Interface Applications” section for more details.
7,
13
VREF-AC0,
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is
only intended to drive its respective VT pin. Maximum sink/source current is ±1.5mA.
Please refer to the “Input Interface Applications” section for more details.
9
/MR
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously
sets the true outputs LOW, complimentary outputs HIGH, and holds them in that state
as long as /MR remains LOW. This input is internally connected to a 25k
pull-up
resistor and will default to logic HIGH state if left open. The input-switching threshold is
VCC/2.
10
CLK_SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs
to the multiplexer. Note that this input is internally connected to a 25k
pull-up resistor
and will default to logic HIGH state if left open. The input-switching threshold is VCC/2.
20, 25, 30, 33,
40
41, 48, 50, 55,
62
VCC
Positive Power Supply. Bypass with a 0.1F||0.01F low ESR capacitor as close to
VCC pin as possible.
21, 22
23, 24
26, 27
28, 29
/QC0, QC0
/QC1, QC1
/QC2, QC2
/QC3, QC3
Bank C LVDS differential output pairs controlled by FSELC1 and FSELC0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
31
NC
No connect.
34, 35,
36, 37
38, 39,
42, 43
44, 45,
46, 47
/QD0, QD0
/QD1, QD1
/QD2, QD2
/QD3, QD3
/QD4, QD4
/QD5, QD5
Bank D LVDS differential output pairs controlled by FSELD1 and FSELD0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
51, 52
53, 54
/QA0, QA0
/QA1, QA1
Bank A LVDS differential output pairs controlled by FSELA1 and FSELA0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
56, 57
58, 59
60, 61
/QB0, QB0
/QB1, QB1
/QB2, QB2
Bank B LVDS differential output pairs controlled by FSELB1 and FSELB0. Refer to
“Function Table” for details. Unused output pairs should be terminated with 100
across the differential pair
相关PDF资料 |
PDF描述 |
|---|---|
| SY100EL56VZI TR | IC MUX 2:1 DUAL 3.3V/5V 20-SOIC |
| SY100EL57LZI TR | ID MULTIPLEXER 4:1 DIFF 16-SOIC |
| SY100EL90VZI TR | IC TRANSLATOR 5V/3.3V 20-SOIC |
| SY100EL91LZI TR | IC TRANSLATOR TRIPLE 20-SOIC |
| SY100EL91ZI TR | IC TRANSLATOR TRIPLE 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SY100EL17VZI TR | 功能描述:IC RECEIVER QUAD DIFF 20SOIC RoHS:否 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:100EL 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SY100EL17VZITR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:5V/3.3V QUAD DIFFERENTIAL RECEIVER |
| SY100EL29V | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:5V/3.3V DUAL DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP w/SET AND RESET |
| SY100EL29VZC | 功能描述:IC FLIP FLOP DUAL 3.3V/5V 20SOIC RoHS:否 类别:集成电路 (IC) >> 逻辑 - 触发器 系列:100EL 标准包装:25 系列:74LS 功能:设置（预设）和复位 类型:JK 型 输出类型:差分 元件数:2 每个元件的位元数:1 频率 - 时钟:25MHz 延迟时间 - 传输:20ns 触发器类型:负边沿 输出电流高，低:400µA, 8mA 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 包装:管件 其它名称:74LS11274LS112AN74LS112NDM74LS112N |
| SY100EL29VZC TR | 功能描述:IC FLIP FLOP DUAL 3.3V/5V 20SOIC RoHS:否 类别:集成电路 (IC) >> 逻辑 - 触发器 系列:100EL 标准包装:25 系列:74LS 功能:设置（预设）和复位 类型:JK 型 输出类型:差分 元件数:2 每个元件的位元数:1 频率 - 时钟:25MHz 延迟时间 - 传输:20ns 触发器类型:负边沿 输出电流高，低:400µA, 8mA 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 包装:管件 其它名称:74LS11274LS112AN74LS112NDM74LS112N |
发布紧急采购，3分钟左右您将得到回复。