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参数资料
| 型号： | SY100EP56VK4CTR |
| 厂商： | MICREL INC |
| 元件分类： | 编、解码器及复用、解复用 |
| 英文描述： | 100E SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 2/8页 |
| 文件大小： | 216K |
| 代理商： | SY100EP56VK4CTR |
2
ECL Pro
SY100EP56V
Micrel
PIN DESCRIPTION
Pin
Pin Number
Function
D0a, /D0a
1, 2,
Channel 0 PECL/ECL differential signal inputs. Multiplexing of these two differential inputs is
D0b, /D0b
4, 5
controlled by SEL0, or COM_SEL. The signal inputs include internal 75k
pull-down resistors.
Default condition is LOW when left floating. The input signal should be terminated externally.
See “
Termination” section
D1a, /D1a
6, 7
Channel 1 PECL/ECL differential signal inputs. Multiplexing of these two differential inputs is
D1b, /D1b
9, 10
controlled by SEL1, or COM_SEL. The signal inputs include internal 75k
pull-down resistors.
Default condition is a logic LOW when left floating. The input signal should be terminated
externally. See “
Termination” section
VBB0, VBB1
3, 8
Channel 0 and Channel 1 reference output voltage. This reference is typically used to bias the
unused inverting input for single-ended input applications, or as the termination point for AC–
coupled differential input applications. V
BB reference value is approximately VCC –1.4V, and tracks
V
CC 1:1. Maximum sink/source capability is 0.50mA. For single ended PECL inputs, connect to
the unused input through a 50
resistor. Decouple the V
BB pin with a 0.01F capacitor. For PECL/
LVPECL inputs, the decoupling capacitor is connected to V
CC, since PECL signals are referenced
to V
CC. Leave floating if not used.
VEE
11
Negative Power Supply: For PECL/LVPECL applications, connect to GND.
/Q1, Q1
12, 13
Channel 1 100KEP PECL/ECL compatible differential output. PECL/ECL termination is with a 50
resistor to V
CC–2V. Unused output pairs may be left floating. Unused single-ended outputs must
have a balanced load. For AC-coupled applications, the output stage emitter follower must have a
DC current path to ground. See “
Termination” section.
SEL1, SEL0
15, 17
100KEP PECL/ECL compatible Channel 1 and Channel 0 MUX select control. See “
MUX Select
Truth Table.” Each pin includes an internal 75k
pull-down resistor. Default condition when left
floating is LOW.
COM_SEL
16
100KEP PECL/ECL compatible Channel 1 and Channel 0 Common MUX select control. This is
the common select control pin for both Channels 0 and 1. Includes an internal 75k
pull-down
resistor. Default condition when left floating is LOW. Leave floating when not used.
/Q0, Q0
18, 19
Channel 0 100K EP PECL/ECL compatible differential output. PECL/ECL termination is with a
50
resistor to V
CC –2V. Unused output pairs may be left floating. Unused single-ended outputs
must have a balanced load. For AC–coupled applications, the output stage emitter follower must
have a DC current path to ground. See “
Termination” section.
VCC
14, 20
Positive Power Supply: Both V
CC pins must be connected to the same power supply externally.
Bypass with 0.1
F//0.01F low ESR capacitors.
MUX SELECT TRUTH TABLE
SEL0
SEL1
COM_SEL
Q0, /Q0
Q1, /Q1
XX
H
a
LL
Lb
b
LH
L
b
a
HH
L
a
HL
L
a
b
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| SY100EP56VK4I TR | 功能描述:编码器、解码器、复用器和解复用器 3.3V/5V Dual Differential 2:1 Multiplexer (I Temp) RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray |
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