参数资料
型号: SY100S863JZ TR
厂商: Micrel Inc
文件页数: 1/8页
文件大小: 0K
描述: IC MUX 8-INPUT PECL DIFF 28-PLCC
标准包装: 750
系列: 100S
类型: 多路复用器
电路: 1 x 8:1
独立电路: 1
电压电源: 双电源
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-LCC(J 形引线)
供应商设备封装: 28-PLCC
包装: 带卷 (TR)
其它名称: SY100S863JZTR
SY100S863JZTR-ND
1
SY100S863
Micrel, Inc.
M9999-032406
hbwhelp@micrel.com or (408) 955-1690
FEATURES
s Low skew
s Differential PECL inputs
s Differential cut-off PECL outputs capable of driving
25
load for driving data bus
s Tri-state TTL output
s TTL select and enable input
s Internal 75K
PECL input pull-down resistors
s PECL I/O fully compatible with industry standard
s Available in 28-pin PLCC package
The SY100S863 is a PECL 8:1 multiplexer designed for
use in new, high-performance PECL systems. It has
differential PECL outputs and a standard TTL output. The
TTL select inputs (SEL0, SEL1, SEL2) determine which one
of the eight differential PECL data inputs (D0–D7) is
propagated to the outputs. The enable pin, EN, is provided
for expansion. When EN is at a TTL logic one level, both
PECL and TTL outputs are enabled. When the enable pin
is set to TTL logic zero level, both PECL outputs of the
differential pair are in cut-off and the TTL output is in a
three-state condition.
DESCRIPTION
BLOCK DIAGRAM
8:1
MUX
8
DIFFERENTIAL
PECL
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(17)
(18)
Q
(13) QTTL
(15)
(28)
(2)
(3)
EN
SEL
0
SEL
1
SEL
2
TTL INPUTS
Pin
Function
D0, /D0 – D7, /D7
Differential PECL Input Pairs
Q, /Q
Differential PECL Outputs
QTTL
TTL Output
EN
Enable Input
SEL0,1,2
Select Inputs
PIN NAMES
SY100S863
8-INPUT PECL
DIFFERENTIAL MUX
WITH TTL SELECTS
Rev.: G
Amendment: /0
Issue Date:
March 2006
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