参数资料
型号: SY54020RMGTR
厂商: MICREL INC
元件分类: 时钟及定时
英文描述: LOW SKEW CLOCK DRIVER, QCC16
封装: 3 X 3 MM, LEAD FREE, MLF-16
文件页数: 12/14页
文件大小: 550K
代理商: SY54020RMGTR
Micrel, Inc.
SY54020R
April 2009
7
M9999-041409-A
hbwhelp@micrel.com or (408) 955-1690
Functional Description
Fail-Safe Input (FSI)
The input of this device has a built-in FSI circuit that
senses the input amplitude and latches the output
when the input signal is not present or when its
amplitude drops below 100mVPK (200mVPP), typically
30mVPK. Maximum frequency of the SY54020R is
limited by the FSI function.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low input signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output.
No ringing and no undetermined state will occur at the
output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal close to the FSI threshold. Due
to the FSI function, the propagation delay will depend
upon rise and fall time of the input signal and on its
amplitude. Refer to “Typical Characteristics” for
detailed information.
Interface Applications
For Input Interface Applications, see Figures 4a
through 4f. For CML Output Termination, see Figures
5a through 5d.
CML Output Termination with VCCO 1.2V
For VCCO of 1.2V, Figure 5a, terminate the output
with 50
to1.2V, DC-coupled, not 100 differentially
across the outputs.
If AC-coupling is used, Figure 5d, terminate into 50
to 1.2V before the coupling capacitor and then
connect to a high value resistor to a reference voltage.
Do not AC-couple with internally terminated receiver,
such as 50
ANY-IN input. AC-coupling will offset the
output voltage by 200mV and this offset voltage will
be too low for proper driver operation. Any unused
output pair needs to be terminated when VCCO is
1.2V, do not leave floating.
CML Output Termination with VCCO 1.8V, 2.5V
For VCCO of 1.8V and 2.5V, Figure 5a and Figure 5b,
terminate
with
either
50
to VCCO or 100
differentially across the outputs. See Figure 5c for AC-
coupling.
Input AC-Coupling
The SY54020R input can accept AC-coupling from
any driver. Bypass VT with a 0.1F low ESR capacitor
to VCC, as shown in Figures 4c and 4d. VT has an
internal high impedance resistor divider as shown in
Figure 2a, to provide a bias voltage for AC-coupling.
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