参数资料
型号: SY58022UMI
厂商: Micrel Inc
文件页数: 2/9页
文件大小: 0K
描述: IC CLK BUFFER TRANSLA 1:4 16-MLF
标准包装: 100
系列: Precision Edge®
类型: 扇出缓冲器(分配),变换器
电路数: 1
比率 - 输入:输出: 1:4
差分 - 输入:输出: 是/是
输入: CML,LVDS,LVPECL
输出: LVPECL
频率 - 最大: 5.5GHz
电源电压: 2.375 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘,16-MLF?
供应商设备封装: 16-MLF?(3x3)
包装: 托盘
2
Precision Edge
SY58022U
Micrel, Inc.
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY58022UMG
MLF-16
Industrial
022U with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY58022UMGTR(2) MLF-16
Industrial
022U with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Die are guaranteed at T
A = 25°C, DC electricals only.
2. Tape and Reel.
PACKAGE/ORDERING INFORMATION
Pin Number
Pin Name
Pin Function
1, 4
IN, /IN
Differential Input: This input pair receives the signal to be buffered. Each pin is internally
terminated with 50Ω to the V
T pin. Note that this input will default to an indeterminate state
if left open. See “Input Interface Applications”section.
2
VT
Input Termination Center-Tap: Each input terminates to this pin. The V
T pin provides a
center-tap for each input (IN, /IN) to the termination network for maximum interface
exibility. See “Input Interface Applications”section.
3
VREF-AC
Reference Output Voltage: This output biases to V
CC –1.2V. It is used when AC-coupling
to differentail inputs. Connect V
REF-AC directly to the VT pin. Bypass with 0.01F low ESR
capacitor to V
CC. See “Input Interface Applications” section.
8, 13
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the
pins as possible. A 0.01F capacitor should be as close to the V
CC pin as possible.
5, 16
GND,
Ground. Exposed pad must be connected to a ground plane that is the same potential
Exposed Pad
as the ground pin.
14, 15
/Q0, Q0,
LVPECL Differential Output Pairs: Differential buffered output copy of the input signal. The
11, 12
/Q1, Q1,
output swing is typically 400mV. Proper termination is 50Ω to V
CC–2V at the receiving
9, 10
/Q2, Q2,
end. Unused output pairs may be left oating with no impact on jitter or skew.
6, 7
/Q3, Q3,
See “LVPECL Output Termination”section.
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
IN
VT
VREF-AC
/IN
Q1
/Q1
Q2
/Q2
GND
Q0
/Q0
VCC
GND
/Q3
Q3
VCC
16-Pin QFN
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