参数资料
| 型号： | SY58026UMG TR |
| 厂商： | Micrel Inc |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC MUX DUAL 2:1 LVPECL 32-MLF |
| 标准包装： | 1,000 |
| 系列： | SY58 |
| 类型： | 多路复用器 |
| 电路： | 1 x 2:1 |
| 独立电路： | 2 |
| 电压电源： | 单电源 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，32-MLF? |
| 供应商设备封装： | 32-MLF?（5x5） |
| 包装： | 带卷 (TR) |
| 其它名称： | SY58026UMGTR SY58026UMGTR-ND |
5
Precision Edge
SY58026U
Micrel, Inc.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C; RL = 50 to VCC–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
NRZ Data
5
Gbps
VOUT 400mV
Clock
6
GHz
tpd
Propagation Delay
IN-to-Q
VIN 300mV
160
230
310
ps
SEL-to-Q
100
220
400
ps
tSKEW
Input-to-Input Skew (Within-bank)
Note 8
715
ps
Bank-to-Bank Skew
Note 9
820
ps
Part-to-Part Skew
Note 10
100
ps
tJITTER
Data
Random Jitter (RJ)
Note 11
1psRMS
Deterministic Jitter (DJ)
Note 12
10
psPP
Clock
Cycle-to-Cycle Jitter (RJ)
Note 13
1psRMS
Total Jitter (TJ)
Note 14
10
psPP
Crosstalk-induced Jitter
Channel-to-Channel (Within-bank)
Note 15, Within-bank.
0.7
psRMS
tr, tf
Output Rise/Fall Time 20% to 80%
At full swing.
35
70
110
ps
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. VIN swing 100mV unless otherwise noted.
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 223–1 PRBS pattern
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output
signal.
14. Total jitter definition: with an ideal clock input of frequency - fMAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
AC ELECTRICAL CHARACTERISTICS(7)
TRUTH TABLES
INA0
/INA0
INA1
/INA1
SELA
QA
/QA
01
X
0
1
10
X
0
1
0
XX
0
1
0
1
XX
1
0
1
0
INB0
/INB0
INB1
/INB1
SELB
QB
/QB
01
X
0
1
10
X
0
1
0
XX
0
1
0
1
XX
1
0
1
0
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