参数资料
| 型号： | SY58052UMI TR |
| 厂商： | Micrel Inc |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER DATA/CLOCK 16-MLF |
| 标准包装： | 500 |
| 系列： | Precision Edge® |
| 类型： | 时钟/频率合成器 |
| PLL： | 无 |
| 输入： | CML，PECL |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 10.7GHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘，16-MLF? |
| 供应商设备封装： | 16-MLF?（3x3） |
| 包装： | 带卷 (TR) |
| 其它名称： | SY58052UMITR SY58052UMITR-ND |
2
Precision Edge
SY58052U
Micrel, Inc.
M9999-082010
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
CLK
/CLK
DATA
/DATA
Q
GND
/Q
VTCLK
GND
VCC
VTDATA
/RESET
GND
VCC
16-Pin MLF (MLF-16)
Pin Number
Pin Name
Pin Function
1, 2
CLK, /CLK
Differential Input: This input pair is the clock signal that re-times the data signal at DATA, /DATA.
Each pin of this pair internally terminates to the VTCLK pin to 50. Note that this input will
default to an indeterminate state if left open. See “Input Interface Applications” section.
3, 4
DATA, /DATA
Differential Input: This input pair is the signal to be synchronized by the CLK, /CLK signal. Each
pin of this pair internally terminates to the VTD pin to 50. Note that this input will default to an
indeterminate state if left open. See “Input Interface Applications” section.
5
VTData
Input Termination Center-Tap: Each of the two inputs, DATA, /DATA terminates to this pin. The
VTData pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section.
6
/RESET
TTL/CMOS-Compatible Input: The /RESET input asynchronously forces the Q output to a logic
“0” state whenever it is active low. Possible state changes due to rising edges on CLK, /CLK are
ignored until /RESET goes inactive high.
7, 10, 11, 14, 15
GND
Ground. Exposed pad must be connected to the same potential as the GND pin.
(Exposed Pad)
8, 13
VCC
Positive Power Supply. Bypass with 0.1
F0.01F low ESR capacitors.
12, 9
Q, /Q
Differential Output: This CML output pair is the output of the flip-flop. The Data input is
transferred to the Q output at the rising edge of CLK (falling edge of /CLK). See “Input Interface
Applications” section.
16
VTCLK
Input Termination Center-Tap: Each of the two inputs, CLK, /CLK terminates to this pin. The
VTCLK pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section.
DATA
/DATA
CLK
/CLK
/RESET
Q
/Q
X
XXX
0
1
X
011
QN–1
/QN–1
X
101
QN–1
/QN–1
01
10
1
10
11
0
TRUTH TABLES
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY58052UMI
MLF-16
Industrial
052U
Sn-Pb
SY58052UMITR(2)
MLF-16
Industrial
052U
Sn-Pb
SY58052UMG(3)
MLF-16
Industrial
052U with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY58052UMGTR(2, 3)
MLF-16
Industrial
052U with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY58600U | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:ULTRA-PRECISION DIFFERENTIAL CML LINE DRIVER/RECEIVER WITH INTERNAL TERMINATION |
| SY58600U_07 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:ULTRA-PRECISION DIFFERENTIAL CML LINE DRIVER/RECEIVER WITH INTERNAL TERMINATION |
| SY58600UMG TR | 功能描述:缓冲器和线路驱动器 Ultra-small, ultra-low jitter CML Buffer (I Temp, Green) RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SY58600UMGTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:ULTRA-PRECISION DIFFERENTIAL CML LINE DRIVER/RECEIVER WITH INTERNAL TERMINATION |
| SY58600UMG-TR | 功能描述:IC LINEDRIVER/RCVR CML DIFF 8MLF 制造商:microchip technology 系列:SY58 包装:剪切带（CT） 零件状态:停产 逻辑类型:差分接收器/驱动器 电源电压:3 V ~ 3.6 V 位数:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-VFDFN 裸露焊盘，8-MLF? 供应商器件封装:8-MLF?（2x2） 标准包装:1 |
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