参数资料
| 型号： | SY69753ALHG TR |
| 厂商： | Micrel Inc |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA REC 125MBPS 32TQFP |
| 标准包装： | 1,000 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，ATM OC-3 |
| 输入： | PECL |
| 输出： | PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 155Mbps |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP 裸露焊盘 |
| 供应商设备封装： | 32-EPAD-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | SY69753ALHGTR SY69753ALHGTR-ND |
Micrel, Inc.
SY69753AL
August 2007
6
M9999-082107-E
hbwhelp@micrel.com or (408) 955-1690
Functional Block
Functional Description
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The
clock is phase aligned by a PLL so that it samples the
data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency detector. Output
pulses from the detector indicate the required
direction of phase correction. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage
Controlled Oscillator (VCO), which generates the
recovered clock.
Frequency
stability,
without
incoming
data,
is
guaranteed by an alternate reference input (REFCLK)
that the PLL locks onto when data is lost. If the
Frequency of the incoming signal varies by greater
than approximately 1000ppm with respect to the
synthesizer frequency, the PLL will be declared out of
lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal. This transfer function yields a 30s data
stream of continuous 1's or 0's for random incoming
NRZ data.
Lock Detect
The SY69753AL contains a link fault indication circuit,
which monitors the integrity of the serial data inputs. If
the received serial data fails the frequency test, then
the PLL will be forced to lock to the local reference
clock. This will maintain the correct frequency of the
recovered clock output under loss of signal or loss of
lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by
more than approximately 1000ppm, the PLL will be
declared out of lock. The lock detect circuit will poll the
input data stream in an attempt to reacquire lock to
data. If the recovered clock frequency is determined to
be within approximately 1000ppm, the PLL will be
declared in lock and the lock detect output will go
active.
During the interval when the CDR is not locked onto
the RDIN input, the LFIN output will not be a static
LOW, but will be changing.
.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY69753L | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, 125Mbps, 155Mbps Clock and Data Recovery |
| SY69753L_06 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, 125Mbps, 155Mbps Clock and Data Recovery |
| SY69753L_07 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, 125Mbps, 155Mbps Clock and Data Recovery |
| SY69753LHC | 功能描述:IC CLOCK/DATA RECVRY 3.3V 32TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| SY69753LHG | 功能描述:计时器和支持产品 3.3V 155 Mbps CDR (I Temp, Green/32 pin TQFP) RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
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