参数资料
| 型号： | SY69952ZH TR |
| 厂商： | Micrel Inc |
| 文件页数： | 1/8页 |
| 文件大小： | 0K |
| 描述： | IC TXRX CLOCK RECOVERY 28-SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，ATM 应用 |
| 输入： | PECL |
| 输出： | PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 155.52Mbps |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | SY69952ZHTR SY69952ZHTR-ND |
SY69952
1
Micrel, Inc.
M9999-062805
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
FEATURES
SY69952
A complete ATM compatible single chip Transmitter
and Receiver
Seamless operation with PMC-Sierra PM5345, VLSI
VNS67200, IgT WAC-013-B/WAC-413-A and NEC
PD98402 UNI Processors
Supports clock and data recovery from 51.84Mbps
or 155.52Mbps NRZ or NRZI data stream
155.52MHz clock multiplication from 19.44MHz
source or 51.84MHz clock multiplication from
6.48MHz source
Line Receiver Inputs: No external buffering needed
Differential output buffering
Link Status Indication
Loop-back testing
100K ECL compatible I/O
Single +5 volt power supply
Replacement for Cypress CY7B952
The SY69952 complies with Bellcore, ITU/CCITT and
ANSI specifications
Available in 28-pin SOIC package
Micrel's SY69952 contains fully integrated transmitter
and receiver functions designed to provide clock recovery
and generation for either 51.84Mbit/s OC/STS-1 or
155.52Mbps OC/STS-3 SONET/SDH (SY69952) and ATM
applications.
On-chip clock generation is performed by a low-jitter
phase-locked loop (PLL) allowing use of 19.44MHz
reference for 155.52MHz generation or a 6.48MHz
reference for 51.84MHz generation. Clock recovery is
performed by synchronizing the on-chip VCO directly to
the incoming data stream.
The SY69952 meets the jitter compliance criteria of
Bellcore, ITU/CCITT and ANSI standards. Low jitter is
ensured by Micrel's advanced PLL technology and
positive ECL (PECL) I/O.
Micre's circuit design techniques coupled with
ASSET bipolar technology result in ultra-fast
performance with low noise and low power dissipation.
OC-3/STS-3
CLOCK RECOVERING
TRANSCEIVER
FUNCTIONAL BLOCK DIAGRAM
PLL
x8
REFCLK+
REFCLK-
PLL1+
PLL1-
ROUT+
ROUT-
RIN+
RIN-
TOUT+
TOUT-
RCLK+
RCLK-
RSER+
RSER-
TSER+
TSER-
TCLK+
TCLK-
MODE
PLL2+
PLL2-
LOOP
LFI
CD
Rev.: N
Amendment: /0
Issue Date: June 2005
ASSET is a trademark of Micrel, Inc.
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