参数资料
| 型号： | SY87700LZG |
| 厂商： | Micrel Inc |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 28-SOIC |
| 标准包装： | 27 |
| 系列： | AnyRate® |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，ATM 应用 |
| 输入： | PECL |
| 输出： | PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 175Mbps |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 1089 (CN2011-ZH PDF) |
| 其它名称： | 576-2059-5 SY87700LZG-ND |
SY87700L
4
Micrel, Inc.
M9999-111406
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram generates
a clock that is at the same frequency as the incoming data
bit rate at the Serial Data input. The clock is phase aligned
by a PLL so that it samples the data in the center of the
data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY87700L contains a link fault indication circuit which
monitors the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be forced to
lock to the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss of signal
or loss of lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by more
than approximately 1000ppm, the PLL will be declared out
of lock. The lock detect circuit will poll the input data stream
in an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within approximately
1000ppm, the PLL will be declared in lock and the lock
detect output will go active.
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| VE-J5R-MX-F2 | CONVERTER MOD DC/DC 7.5V 75W |
| SY87700VHH | IC CLOCK/DATA RECOVERY 32-TQFP |
| MS27505E11F99PA | CONN RCPT 7POS BOX MNT W/PINS |
| VE-J5R-MX-F1 | CONVERTER MOD DC/DC 7.5V 75W |
| SY87700ALZG | IC CLOCK/DATA RECOVERY 28-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SY87700LZG TR | 功能描述:计时器和支持产品 3.3V 32Mbps-175Mbps CDR (I Temp, Green/28 SOIC/T+R) RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| SY87700LZGTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87700AL for new designs |
| SY87700LZI | 功能描述:IC CLOCK/DATA RECOVERY 28-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:AnyRate® 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| SY87700LZITR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700V | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:5V/3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
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