参数资料
型号: SY87725LHY TR
厂商: Micrel Inc
文件页数: 1/20页
文件大小: 0K
描述: IC TRANSCEIVER SGL CHIP 64-TQFP
标准包装: 1,000
类型: 收发器
规程: LVDS
电源电压: 3.15 V ~ 3.45 V
安装类型: 表面贴装
封装/外壳: 64-TQFP 裸露焊盘
供应商设备封装: 64-EP-TQFP
包装: 带卷 (TR)
其它名称: SY87725LHYTR
SY87725LHYTR-ND
SY87725L
2.5Gbps GPON/BPON ONU SERDES
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
July 2007
M9999-071007-B
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY87725L is a single chip transceiver for data rates
up to 2.5Gbps. On the receive side, it includes a
complete clock recovery and data retiming circuit with
an integrated 4-bit serial-to-parallel data converter. On
the transmit side, it includes a synthesizer with an
integrated 4-bit parallel-to-serial data converter.
The SY87725L receiver has a synthesizer that
generates an internal clock from an externally supplied
TTL or PECL REFCLK that can be either 155.52MHz or
77.76MHz. This internal clock can be used by the clock
recovery PLL if an absence of transitions on the input
serial data stream prevents normal clock recovery. This
enables it to provide a stable clock source in the
absence of transitions on the incoming serial data
stream.
The transmit synthesizer uses the CLKIN parallel data
clock to generate its own serial rate clock locked to
CLKIN. This enables the transmit and receive to operate
at different data rates.
The serial interface for both the transmit and receive
functions feature industry standard high-speed
differential CML I/O. The parallel interfaces feature high-
speed LVDS I/O with an internal 100 termination on
the LVDS inputs.
The first bit for the serial-to-parallel conversion can be
moved using the RCV_SYNC input. The RCV_SYNC
input enables the parallel word boundary to move up in
time by one bit time for each pulse. This allows it to in
effect “swallow” one bit each time the RCV_SYNC pulse
is asserted.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
Single 3.3V supply and 1W typ. power consumption
2.5G/1.25G/625Mbps down stream
1.25G/625M/156Mbps up stream
4-bit Serdes with LVDS interfaces
Serial Data input sensitivity of 30mV typical
Training mode for fast lock acquisition
Link Fault Indicator (LFIN: “HIGH” = Locked)
Separate training and MUX synthesizers
Loop back function for diagnostics
TTL–CML Translator for MAC-to-Laser diode driver
burst control
Selectable double data rate option for low cost
FPGA/ASIC MAC implementation
Available in Pb-Free (10mm x 10mm) 64-pin
EPAD-TQFP
Applications
BPON/GPON/GEPON/EPON
Markets
FTTH/FTTP
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