参数资料
| 型号： | SY87813LHG TR |
| 厂商： | Micrel Inc |
| 文件页数： | 5/15页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-TQFP |
| 标准包装： | 1,000 |
| 系列： | AnyRate® |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，ATM 应用 |
| 输入： | PECL |
| 输出： | PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.3Gbps |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP 裸露焊盘 |
| 供应商设备封装： | 32-EPAD-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | SY87813LHGTR SY87813LHGTR-ND |
Micrel, Inc.
SY87813L
November 2006
13
M9999-112806-B
hbwhelp@micrel.com or (408) 955-1690
Appendix A
Layout and General Suggestions
1.
Establish controlled impedance stripline, microstrip, or
coplanar construction techniques.
2.
Signal paths should have approximately the same width
as the device pads.
3.
All differential paths are critical timing paths, where
skew should be matched to within ±10ps.
4.
Signal trace impedance should not vary more than
±5%. If in doubt, perform TDR analysis of all high-speed
signal traces.
5.
Maintain compact filter networks as close to filter pins
as possible. Provide ground plane relief under filter path
to reduce stray capacitance. Be careful of crosstalk
coupling into the filter network.
6.
Maintain low jitter on the REFCLK input. Isolate the
XTAL oscillator from power supply noise by adequately
decoupling. Keep XTAL oscillator close to device, and
minimize capacitive coupling from adjacent signals.
7.
Higher speed operation may require use of
fundamental-tone (third-overtone typically has more
jitter) crystal-based oscillator for optimum performance.
Evaluate and compare candidates by measuring
TXCLK jitter.
8.
All unused outputs must be terminated. To conserve
power, unused PECL outputs can be terminated with a
1k resistor to VEE.
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