参数资料
型号: SY88309BLMG
厂商: Micrel Inc
文件页数: 9/11页
文件大小: 0K
描述: IC AMP PECL LIMITING POST 16-MLF
标准包装: 100
放大器类型: 限制
电路数: 1
输出类型: 差分
电流 - 电源: 38mA
电流 - 输出 / 通道: 50mA
电压 - 电源,单路/双路(±): 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘,16-MLF?
供应商设备封装: 16-QFN-EP(3x3)
包装: 管件
产品目录页面: 1089 (CN2011-ZH PDF)
其它名称: 576-3055
Micrel, Inc.
SY88309BL
November 2007
7
M9999-111507-C
hbwhelp@micrel.com or (408) 955-1690
Functional Block Diagram
Detailed Description
The SY88309BL low-power limiting post amplifiers
operate from a single +3.3V power supply, over
temperatures from –40
oC to +85oC. Signals with data
rates up to 3.2Gbps and as small as 10mVpp can be
amplified. Figure 1 shows the allowed input voltage
swing. The SY88309BL generates an SD output
allowing feedback to EN for output stability. SDLVL sets
the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the input
stage. The high-sensitivity of the input amplifier allows
signals as small as 10mVpp to be amplified. The input
amplifier also allows input signals as large as
1800mVPP. Input signals below 12mVPP are linearly
amplified with a typical 42dB differential voltage gain.
Since it is a limiting amplifier, these devices output
typically 1500mVPP voltage-limited waveforms for input
signals greater than 12mVPP. Applications requiring the
SY88309BL to operate with strong signals should have
the upstream TIA placed as close as possible to the
devices’ input pins. This ensures the best performance
of the device.
Output Buffer
The SY88309BL PECL output buffers are designed to
drive 50 lines. The output buffer requires appropriate
termination for proper operation. An external 50
resistor to VCC-2V for each output pin provides this.
Figure 3 shows a simplified schematic of the output
stage.
Signal Detect
The SY88309BL generates a chatter-free SD open-
collector TTL output, as shown in Figure 4. SD asserts
high if the input amplitude rises above the threshold sets
by SDLVL and de-asserts low otherwise. The SD output
can be fed back to the EN input to maintain stability
Signal-Detect Level Set
Programmable SD level set pin (SDLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between VCC and SDLVL set the
voltage at SDLVL. This voltage ranges from VCC to VREF.
The external resistor creates a voltage divider between
VCC and VREF, as shown in Figure 5.
Hysteresis
The SY88309BL typically provide 3.5dB SD electrical
hysteresis. By definition, a power ratio measured in dB
is 10log (power ratio). Power is calculated as V
2
IN/R for
an electrical signal. Hence, the same ratio can be stated
as 20log (voltage ratio). While in linear mode, the
electrical voltage input changes linearly with the optical
power and therefore, the ratios change linearly. Thus,
the optical hysteresis in dB is half the electrical
hysteresis in dB given in the data sheet. Since the
SY88309BL are electrical devices, this data sheet refers
to hysteresis in electrical terms. With 3.5dB SD
hysteresis, a voltage factor of 1.5 is required to assert or
de-assert SD.
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