参数资料
型号: SY88343BLMG
厂商: Micrel Inc
文件页数: 8/10页
文件大小: 0K
描述: IC AMP LIMIT CML TTL SIG 16MLF
标准包装: 100
放大器类型: 限制
电路数: 1
输出类型: 差分
电流 - 电源: 45mA
电流 - 输出 / 通道: 50mA
电压 - 电源,单路/双路(±): 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘,16-MLF?
供应商设备封装: 16-QFN-EP(3x3)
包装: 管件
Micrel, Inc.
SY88343BL
February 2007
7
M9999-021707-B
hbwhelp@micrel.com or (408) 955-1690
Functional Block Diagram
Detailed Description
The
SY88343BL
low-power
limiting
post
amplifier
operates from a single +3.3V power supply, over
temperatures from –40
oC to +85oC. Signals with data
rates up to 3.2Gbps and as small as 5mVPP can be
amplified. Figure 1 shows the allowed input voltage
swing. The SY88343BL generates a LOS output
allowing feedback to /EN for output stability. LOSLVL sets
the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
Figure
2
shows
a
simplified
schematic
of
the
SY88343BL’s input stage. The high-sensitivity of the
input amplifier allows signals as small as 5mVPP to be
detected and amplified. The input amplifier also allows
input signals as large as 1800mVPP. Input signals are
linearly amplified with a typical 38dB differential voltage
gain. Since it is a limiting amplifier, the SY88343BL
outputs typically 800mVPP voltage-limited waveforms for
input signals that are greater than 12mVPP. Applications
requiring the SY88343BL to operate with high-gain
should have the upstream TIA placed as close as
possible to the SY88343BL’s input pins. This ensures
the best performance of the device.
Output Buffer
The SY88343BL’s CML output buffer is designed to
drive 50
lines. The output buffer requires appropriate
termination for proper operation. An external 50
resistor to VCC for each output pin provides this. Figure 3
shows a simplified schematic of the output stage.
Loss-of-Signal
The SY88343BL generates a chatter-free LOS open-
collector TTL output with an internal 4.75k
pull-up
resistor, as shown in Figure 4. LOS is used to determine
that the input amplitude is large enough to be
considered a valid input. LOS asserts high if the input
amplitude falls below the threshold set by LOSLVL and
de-asserts low otherwise. LOS can be fed back to the
enable bar (/EN) input to maintain output stability under
a loss of signal condition. /EN de-asserts the true output
signal without removing the input signals. Typical, 3.5dB
LOS hysteresis is provided to prevent chattering.
Loss-of-Signal Level Set
A programmable LOS level set pin (LOSLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between VCC and LOSLVL sets the
voltage at LOSLVL. This voltage ranges from VCC to VREF.
The external resistor creates a voltage divider between
VCC and VREF, as shown in Figure 5.
Hysteresis
The SY88343BL provides typically 3.5dB LOS electrical
hysteresis. By definition, a power ratio measured in dB
is 10log (power ratio). Power is calculated as V
2
IN/R for
an electrical signal. Hence, the same ratio can be stated
as 20log (voltage ratio). While in linear mode, the
electrical voltage input changes linearly with the optical
power and therefore the ratios change linearly. Thus,
the optical hysteresis in dB is half the electrical
hysteresis in dB given in the data sheet. Since the
SY88343BL is an electrical device; this data sheet refers
to hysteresis in electrical terms. With 3.5dB LOS
hysteresis, a voltage factor of 1.5 is required to assert or
de-assert LOS.
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