参数资料
型号: SY88345BLMG
厂商: Micrel Inc
文件页数: 6/10页
文件大小: 0K
描述: IC POST AMP CML LP LIMIT 16-MLF
标准包装: 100
类型: 限幅后置放大器
应用: 光纤学网络
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘,16-MLF?
供应商设备封装: 16-MLF?(3x3)
包装: 管件
Micrel, Inc.
SY88345BL
February 2007
5
M9999-021207-B
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCC = 3.0V to 3.6V; RLOAD = 50
to V
CC; TA = –40°C to +85°C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
tr, tf
Output Rise/Fall Time
(20% to 80%)
Note 4
60
120
ps
tJITTER
Deterministic
Random
Note 5
Note 6
15
5
psPP
psRMS
VID
Differential Input Voltage Swing
Figure 1
5
1800
mVPP
VOD
Differential Output Voltage Swing
VID > 10mVPP Figure 1
700
800
950
mVPP
TOFF
SD De-assert Time
2
10
s
TON
SD Assert Time
2
10
s
SDAL
Low SD Assert Level
RSDLVL = 15k
, Note 8
4.5
mVPP
SDDL
Low SD De-assert Level
RSDLVL = 15k
, Note 8
3.0
mVPP
HYSL
Low SD Hysteresis
RSDLVL = 15k
, Note 7
3.5
dB
SDAM
Medium SD Assert Level
RSDLVL = 5k
, Note 8
7.5
11
mVPP
SDDM
Medium SD De-assert Level
RSDLVL = 5k
, Note 8
2
5.0
mVPP
HYSM
Medium SD Hysteresis
RSDLVL = 5k
, Note 7
2
3.5
4.5
dB
SDAH
High SD Assert Level
RSDLVL = 100
, Note 8
18
23
mVPP
SDDH
High SD De-assert Level
RSDLVL = 100
, Note 8
8
12
mVPP
HYSH
High SD Hysteresis
RSDLVL = 100
, Note 7
2
3.5
4.5
dB
B-3dB
3dB Bandwidth
2
GHz
AV(Diff)
Differential Voltage Gain
32
38
dB
S21
Single-ended Small-Signal Gain
26
32
dB
Notes:
4. Amplifier in limiting mode. Input is a 200MHz square wave.
5. Deterministic jitter measured using 3.2Gbps K28.5 pattern, VID = 10mVPP.
6. Random jitter measured using 3.2Gbps K28.7 pattern, VID = 10mVPP.
7. This specification defines electrical hysteresis as 20log (SD Assert/SD De-assert). The ratio between optical hysteresis and
electrical hysteresis is found to vary between 1.5 and 2, depending upon the level of received optical power and ROSA
characteristics. Based upon that ratio, the optical hysteresis corresponding to the electrical hysteresis range 2dB-4.5dB, as
shown in the AC characteristics table, will be 1dB-3dB.
8. See “Typical Operating Characteristics” for a graph showing how to choose a particular RSDLVL for a particular SD assert and its
associated de-assert amplitude.
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