参数资料
| 型号： | SY89296UTI TR |
| 厂商： | Micrel Inc |
| 文件页数： | 5/17页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-TQFP |
| 标准包装： | 1,000 |
| 系列： | Precision Edge® |
| 标片/步级数： | 1024 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 3.2ns |
| 接头增量： | 10ps |
| 可用的总延迟： | 3.2ns ~ 14.8ns |
| 独立延迟数： | 1 |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP |
| 包装： | 带卷 (TR) |
| 其它名称： | SY89296UTITR SY89296UTITR-ND |
Micrel, Inc.
SY89296U
November 2011
13
M9999-112211
hbwhelp@micrel.com or (408) 955-1690
Application Information
For best performance, use good high frequency layout
techniques, filter VCC supplies, and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the SY89296U data inputs and outputs.
VBB Reference
The VBB pin is an internally generated reference and is
available for use only by the SY89296U. When unused,
this pin should be left unconnected. The two common
uses for VBB are to handle a single-ended PECL input,
and to re-bias inputs for AC-coupling applications.
If either IN or /IN is driven by a single-ended output, VBB
is used to bias the unused input. Please refer to Figure
10. The PECL signal driving the SY89296U may
optionally be inverted in this case.
When the signal is AC-coupled, VBB is used, as shown in
Figure 13, to re-bias IN and/or /IN. This ensures that
SY89296U inputs are within acceptable common mode
range.
In all cases, VBB current sinking or sourcing must be
limited to 0.5mA or less.
Setting D Input Logic Thresholds
In all designs where the SY89296U GND supply is at
zero volts, the D inputs can accommodate CMOS and
TTL level signals, as well as PECL or LVPECL. Figures
11, 12, and 14 show how to connect VCF and VEF for all
possible cases.
Cascading
Two or more SY89296U may be cascaded in order to
extend the range of delays permitted. Each additional
SY89296U adds about 3.2ns to the minimum delay and
adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY89296U. Using this internal circuitry, the SY89296U
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY89296U appear in
Figures 7, 8, and 9.
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相关代理商/技术参数 |
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| SY89297U | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5/3.3V, 3.2Gbps Precision CML |
| SY89297UMG | 功能描述:延迟线/计时元素 2.5/3.3V Dual Channel Delay Line with 5ps Step Delay (improved SY89295), Industrial, Recommended for New Designs RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| SY89297UMG TR | 功能描述:延迟线/计时元素 2.5/3.3V Dual Channel Delay Line with 5ps Step Delay (improved SY89295), Industrial, Recommended for New Designs RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| SY89297UMGTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:2.5/3.3V, 3.2Gbps Precision CML |
| SY89297UMH | 功能描述:延迟线/计时元素 2.5V Dual Channel Delay Line with 5ps Step Delay (improved SY89295) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
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