参数资料
型号: SY89426JY
厂商: Micrel Inc
文件页数: 2/7页
文件大小: 0K
描述: IC SYNTHESIZER CLK SONET 28-PLCC
标准包装: 38
系列: Precision Edge®
类型: 时钟/频率合成器
PLL:
输入: TTL
输出: PECL,TTL
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 无/是
频率 - 最大: 622.08MHz
除法器/乘法器: 是/无
电源电压: 4.75 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-LCC(J 形引线)
供应商设备封装: 28-PLCC
包装: 管件
2
Precision Edge
SY89426
Micrel, Inc.
M9999-112105
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
28-Pin PLCC (J28-1)
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89426JC
J28-1
Commercial
SY89426JC
Sn-Pb
SY89426JCTR(2)
J28-1
Commercial
SY89426JC
Sn-Pb
SY89426JY(3)
J28-1
Industrial
SY89426JY with
Matte-Sn
Pb-Free bar line indicator
Pb-Free
SY89426JYTR(2, 3)
J28-1
Industrial
SY89426JY with
Matte-Sn
Pb-Free bar line indicator
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24
23
22
21 20
19
56
7
8
9
10
11
GND
NC
GND
NC
VCC
FLTRP
RST
RETRFCK
V
CC
V
CC
DISC
FLTRN
PLCC
TOP VIEW
J28-1
VCC
CK622P
CK622N
VCCO
CK155
GND
SEL39
RFCK
VCC
NC
SEL78
INPUTS
RFCK [Reference Clock] TTL
Reference clock IN. (38.88, 51.84 or 77.76MHz).
SEL39 [38.88MHz Select] TTL
Logic HIGH on this pin denotes a 38.88MHz input reference
clock. Tie to logic LOW if input is not 38.88MHz.
SEL78 [77.76MHz Select] TTL
Logic HIGH on this pin denotes a 77.76MHz input reference
clock. Tie to logic LOW if input is not 77.76MHz.
RST [Reset] TTL
Tie to logic LOW for normal operation; logic HIGH forces reset
of internal Phase Detector & feedback dividers.
FLTRP, FLTRN [Loop Filter, Pos & Neg] Analog
Connect a series RC loop filter between these pins. The
suggested RC values are 500
and 0.1F, as shown in the
Typical Application.
DISC [Disable Clock] TTL
Logic HIGH on this pin disables the Retimed Reference Clock
output RETRFCK); if this output is not required, it is
recommended that it be disabled to reduce switching noise. A
logic LOW enables the output.
PIN DESCRIPTION
OUTPUTS
CK622P, CK622N [622 Clock Output] Differential PECL.
622.08MHz output clock from PLL B.
CK155 [155 Clock Out] Single-ended PECL
155.52MHz output clock.
RETRFCK [Retimed Reference Clock Out] TTL
An output clock with the same frequency as the input Reference
Clock (RFCK) and a 45-55% duty cycle. This output is derived
by dividing the 622.08MHz output by the appropriate factor
(e.g., divide by 16 for a 38.88MHz inout reference; divide by
12 for 51.84Mhz in; or divide by 8 for 77.76MHz in).
POWER & GROUND
VCC
+5V for internal circuits.
VCCO
+5V for PECL outputs.
GND
Ground (0 volts).
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