参数资料
型号: SY89430VJZ
厂商: Micrel Inc
文件页数: 5/11页
文件大小: 0K
描述: IC SYNTHESIZER FREQ PROGR 28PLCC
标准包装: 38
系列: Precision Edge®
类型: 频率合成器
PLL:
输入: 晶体
输出: PECL
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 无/是
频率 - 最大: 950MHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 5.25 V
工作温度: 0°C ~ 75°C
安装类型: 表面贴装
封装/外壳: 28-LCC(J 形引线)
供应商设备封装: 28-PLCC
包装: 管件
产品目录页面: 1090 (CN2011-ZH PDF)
其它名称: 576-2560
SY89430VJZ-ND
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA805 Rev. 1.0.0
3
FSA805
USB2.0
High-Speed
(480Mbps),
UART,
a
nd
Audio
Switch
with
Negative
Signal
Capability
Functional Description
The FSA805 USB2.0 accessory switch is designed to
consolidate wired accessories for portable devices, such
as cellular telephones and portable audio players. The
benefits of consolidation include reduced space
requirements from a reduction of connectors and their
size. The micro-USB connector, for example, reduces
connector height and depth, allowing for slimmer overall
designs. Using the USB industry standard and a
common connector type for devices such as chargers
and headsets, greatly reduces the waste associated with
new phone purchases by allowing re-use of the devices.
Using just five wires for all connection types
considerably reduces the cost of wired accessories and
simplifies their construction. The FSA805 facilitates
adopting this methodology because it is designed to
redirect the DP/DM pins from the USB connector to one
of three ports at the baseband’s discretion.
Applications with Multiple USB Controllers
The FSA805 UART port (RxD_HOST, TxD_HOST) can
be used as a High-speed USB interface. This allows it to
operate in an application with two USB controllers (one
full speed, and the other full or high speed).
In this configuration, it is recommended to configure the
switches to OPEN before switching to the other (second)
USB interface. The OPEN setting duration should be
long enough for the accessory to go to a SE0 state, so
when the switch is set to the other (second) USB port,
the new controller re-enumerates.
Mode Descriptions
The FSA805 has two select pins to control the switching
operations, SEL[0], and SEL[1]. Table 1 describes mode
operation.
Table 1.
Selection Truth Table
SEL[1]
SEL[0]
Switch Action
Description
0
OPEN
Open all switch paths (device in low-power mode)
(1)
0
1
USB, UART
Closes USB/UART1 path to D+/D-, default condition
(2)
- DP_CON connected to RxD_HOST
- DM_CON connected to TxD_HOST
1
0
USB, UART
Closes USB/UART2 path to D+/D-
- DP_CON connected to DP_HOST
- DM_CON connected to DM_HOST
1
AUDIO
Closes audio path to D+/D- only
- DP_CON connected to R_HOST
- DM_CON connected to L_HOST
Notes:
1.
When the audio switch is in the OPEN position (Table 1, line1), the R and L are terminated to GND with internal
termination resistors to discharge any stray capacitance that could cause audio pop.
2.
The SELECT pins are CMOS inputs and should not be left in a floating condition. Some applications require the
UART path be in the CLOSED position on power-up for initial programming of the device under test. If that
condition is desired, the two SELECT pins should be pulled to the correct levels with external resistors that
should exceed 100K
to reduce the static power consumption. In other applications, adding weak pull-down
resistors to GND defaults the device to all paths open (low-power mode).
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