参数资料
型号: SY89474UMG TR
厂商: Micrel Inc
文件页数: 8/11页
文件大小: 0K
描述: IC MUX 2:1 LVDS 1:2 FANOUT 24MLF
标准包装: 1,000
系列: SY89
类型: 多路复用器
电路: 1 x 2:1
独立电路: 1
电压电源: 单电源
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘,24-MLF?
供应商设备封装: 24-MLF?(4x4)
包装: 带卷 (TR)
其它名称: SY89474UMGTR
SY89474UMGTR-ND
Micrel, Inc.
SY89474U
August 2005
6
M9999-081105
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
(7)
VCC = 2.5V ±5%; TA = -40°C to + 85°C; RL = 100 across output pair; unless otherwise stated
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
2.5
3.2
Gbps
fMAX
Maximum Operating Frequency
VOUT ≥ 200mV
Clock
2.5
4
GHz
220
320
470
ps
tpd
Differential Propagation Delay In-to-Q
SEL-to-Q
VTH = VCC/2
200
350
550
ps
tpd
Tempco
Differential Propagation Delay
Temperature Coefficient
158
fs/
oC
Output-to-Output Skew
Note 8
5
20
ps
tSKEW
Part-to-Part Skew
Note 9
200
ps
Note 10
1
psRMS
Data
Random Jitter
Deterministic Jitter
Note 11
10
psPP
Clock
Cycle-to-cycle Jitter
Note 12
1
psRMS
Total Jitter
Note 13
10
psPP
tJitter
Crosstalk-Induced Jitter
Note 14
0.7
psRMS
tr, tf
Output Rise/Fall Time (20% to 80%)
At full output swing.
30
150
ps
Notes:
7.
High-frequency AC-parameters are guaranteed by design and characterization.
8.
Output-to-output skew is measured between two different outputs under identical transitions.
9.
Part-to-part skew is defined for two parts with identical power supply voltages, at the same temperature, and with no skew of the edges at
the respective inputs.
10. Random Jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
11. Deterministic Jitter is measured with both K28.5 and 2
23-1 PRBS pattern, measured at ≤ fMAX.
12. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
13. Total Jitter definition: With an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.
14. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
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