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参数资料
| 型号： | SY89533LHZ |
| 厂商： | MICREL INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 622.08 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| 封装： | LEAD FREE, TQFP-64 |
| 文件页数： | 14/15页 |
| 文件大小： | 187K |
| 代理商： | SY89533LHZ |
8
Precision Edge
SY89532/33L
Micrel, Inc.
M9999-010808
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
At the core of the SY89532/33L clock synthesizer is a
precision PLL driven by 14MHz to 18MHz series resonant
crystal. For users who wish to supply a TTL or LVPECL clock
input, please use the SY89534L or SY89535L. The PLL
output is sent to three banks of outputs. Each bank has its own
programmable frequency divider, and the design is optimized
to provide very low skew between banks, and very low jitter.
PLL Programming and Operation
IMPORTANT: If the internal VCO will be used, VCO_SEL
must be tied LOW, and ExtVCO pins can be left unconnected.
The internal VCO range is 600MHz to 1000MHz, and the
feedback ratio is selectable via the MSEL divider control (M3:0
pins). If the designer wishes to use the internal VCO, the
VCO_SEL pin must be tied low. The feedback ratio can be
changed without powering the chip down. The PLL output is
fed to three banks of outputs: Bank A, Bank B, and Bank C.
Banks A and C each have two differential LVPECL output
pairs. Bank B has nine differential output pairs. On the
SY89532L, Bank B is LVPECL. On the SY89533L, Bank B is
LVDS.
Each bank has a separate frequency divider circuit that can
be reprogrammed on the fly. The FSEL_x0:2 (where x is A,B,
or C) pins control the divider value. The FSEL divider can be
programmed in ratios from 2 to 18, and the outputs of Banks
A,B, and C can be synchronized after programming by pulsing
the OUT_SYNC pin HIGH-LOW-HIGH.
To determine the correct settings for SY89532/33L follow
these steps:
1. Refer to the "Suggested Selections for Specific
Customer Applications" section for common applications,
as well as the formula used to compute the output
frequency.
2. Determine the desired output frequency, such as
66MHz.
3. Choose a crystal frequency between 14MHz and 18MHz.
In this example, we choose 18MHz for the crystal
frequency. This results in an input/output ratio of 66/18.
4. Refer to the "Feedback Divide Select Table" and the
"Post-Divide Frequency Select Table" to find values for
MSEL and FSEL such that MSEL/FSEL equals the same
66/18 ratio. In this example, values of MSEL=44 and
FSEL=12 work.
5. Make sure that XTAL (the crystal frequency) multiplied
by MSEL is between 600MHz and 1000MHz.
The user may need to experiment with different crystal
frequencies to satisfy these requirements.
External VCO Operation
If the designer wishes to use an external VCO, the VCO_SEL
pin can be left floating or tied HIGH, and the external VCO
signal is connected to the ExtVCO differential input pair. The
ExtVCO input structure is designed to accept many popular
logic types. See “Input Interface for ExtVCO Pins” section for
interface diagrams. A SONET OC-48 compliant 622.08MHz
clock is a good example of an application requiring an external
VCO. For this application, use a VCXO to supply the
1244.16MHz. to the ExtVCO pins, and set VCO_SEL to HIGH.
To save power and reduce noise, the internal VCO is shut
down when VCO_SEL is HIGH.
ExtVCO Input Interface
The flexible ExtVCO inputs are designed to accept any
differential or single-ended input signal within 300mV above
VCC and 300mV below ground.
Do not leave unused ExtVCO inputs floating. Tie either the
true or complement inputs to ground, but not both. A logic zero
is achieved by connecting the complement input to ground
with the true input floating. For a TTL input, tie a 2.5k
resistor
between the complement input and ground. See “Input Interface
for ExtVCO Pins” section, Figures 5a through 5j.
Input Levels
LVDS, CML and HSTL differential signals may be connected
directly to the ExtVCO inputs. Depending on the actual worst
case voltage seen, the minimum input voltage swing varies as
illustrated in the following table:
Input Voltage Range
Minimum Voltage Swing
0 to 2.4V
100mV
0 to VCC +0.3
200mV
R2
1.5k
R2
1.5k
R1
1.05k
R1
1.05k
GND
EXTVCO
VCC
/EXTVCO
Figure 1. Simplified Input Structure
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SY89533LHZ TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:Precision Edge® 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| SY89533LHZTR | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER |
| SY89534L | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89534L_08 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER |
| SY89534LHC | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:Precision Edge® 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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