参数资料
型号: SY89809LTC TR
厂商: Micrel Inc
文件页数: 1/8页
文件大小: 0K
描述: IC CLOCK BUFFER MUX 2:9 32-TQFP
标准包装: 1,000
系列: Precision Edge®
类型: 扇出缓冲器(分配),多路复用器
电路数: 1
比率 - 输入:输出: 2:9
差分 - 输入:输出: 是/是
输入: HSTL,LVPECL
输出: HSTL
频率 - 最大: 500MHz
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP
包装: 带卷 (TR)
其它名称: SY89809LTCTR
SY89809LTCTR-ND
SY89809L
3.3V 1:9 High-Performance, Low-Voltage
Bus Clock Driver
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
December 2009
M9999-121409-D
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89809L is a High-Performance Bus Clock Driver
with 9 differential HSTL (High-Speed Transceiver Logic)
output pairs. The part is designed for use in low-voltage
(3.3V/1.8V) applications, which require a large number of
outputs to drive precisely aligned, ultra-low skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous
so
that
the
outputs
will
only
be
enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse
when the device is enabled/disabled as can happen with
an asynchronous control.
The SY89809L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)—performance
previously unachievable in a standard product having such
a high number of outputs. The SY89809L is available in a
single space saving package, enabling a lower overall cost
solution.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Logic Symbol
Precision Edge
Features
3.3V core supply, 1.8V output supply for reduced power
LVPECL and HSTL inputs
9 differential HSTL (low-voltage swing) output pairs
HSTL outputs drive 50-to-ground with no offset voltage
500MHz maximum clock frequency
Low part-to-part skew (200ps max.)
Low pin-to-pin skew (50ps max.)
Available in 32-pin TQFP
Applications
High-performance PCs
Workstations
Parallel processor-based systems
Other high-performance computing
Communications
Level
Direction
Signal
HSTL
Input
HSTL_CLK, /HSTL_CLK
HSTL
Output
Q0 – Q8, /Q0 – /Q8
LVPECL
Input
LVPECL_CLK, /LVPECL_CLK
LVCMOS/LVTTL
Input
CLK_SEL, OE
Table 1. Signal Groups
OE
(1)
CLK_SEL
Q0 – Q8
/Q0 – /Q8
0
LOW
HIGH
0
1
LOW
HIGH
1
0
HSTL_CLK
/HSTL_CLK
1
LVPECL_CLK
/LVPECL_CLK
Table 2. Truth Table
Note:
1. The OE (output enable) signal is synchronized with the low level of
the HSTL_CLK and LVPECL_CLK signal.
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