参数资料
型号: SY89852UMG
厂商: Micrel Inc
文件页数: 10/13页
文件大小: 0K
描述: IC MUX 2:1 LVPECL DIFF LP 16-MLF
标准包装: 100
系列: SY89
类型: 多路复用器
电路: 1 x 2:1
独立电路: 1
电压电源: 单电源
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘,16-MLF?
供应商设备封装: 16-MLF?(3x3)
包装: 管件
产品目录页面: 1090 (CN2011-ZH PDF)
其它名称: 576-2099-5
SY89852UMG-ND
Micrel, Inc.
SY89852U
October 2008
M9999-100208-D
hbwhelp@micrel.com or (408) 955-1690
6
AC Electrical Characteristics
(8)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, RL = 50
to V
CC –2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
NRZ Data
2.5
3.2
Gbps
Clock, VOUT
≥ 400mV
2.5
3.5
GHz
tPD
Propagation Delay
IN-to-Q, /IN-to-Q
SEL-to-Q
VIN
≥ 100mV
140
100
230
250
340
400
ps
tPD
Tempco
Differential Propagation Delay Temperature
Coefficient
100
fs/
oC
tJitter
Data
Random Jitter (RJ)
Note 9
1
psRMS
Deterministic Jitter (DJ)
Note 10
10
psRMS
Clock
Cycle-to-Cycle Jitter
Note 11
1
psPP
Total Jitter
Note 12
10
psRMS
Crosstalk-induced Jitter
Note 13
0.7
psRMS
tr, tf
Output Rise/Fall Time (20% to 80%)
At full output swing.
50
100
180
ps
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps.
10. DJ is measured at 2.5Gbps, with both K28.5 and 2
23 – 1 PRBS pattern.
11. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
12. Total jitter definition: With an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
13. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output
while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs.
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