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参数资料
| 型号： | SYS8V512FK-035 |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 MULTI DEVICE SRAM MODULE, 35 ns, PDMA32 |
| 封装： | PLASTIC, DIP-32 |
| 文件页数： | 1/2页 |
| 文件大小： | 45K |
| 代理商： | SYS8V512FK-035 |
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Power (+5V)
A0 ~ A18
D0 ~ D7
CS
WE
OE
V
CC
GND
Ground
Package Details
Block Diagram
Pin Functions
Pin Definition
Description
Features
Access Times of 015/020/025/35 ns.
32 Pin 0.6" Dual-In-Line package with JEDEC
compatible pinout.
3.3 Volt Supply ± 10%.
Low Power Dissipation:
Operating
6.60 mW (maximum).
Standby (
-L Version
) 0.80 W (maximum).
Completely Static Operation.
Equal Access and Cycle Times.
All Inputs and Outputs Directly TTL
compatible
On-board Supply Decoupling Capacitors.
Issue 1.3 : February 1999
SYS8V512FK - 015/020/025/35
512K x 8 SRAM MODULE
AO - A 16
D0 - D7
OE
CS
128K x 8
SRAM
WE
128K x 8
SRAM
CS
128K x 8
SRAM
CS
128K x 8
SRAM
CS
DECODER
A17
A18
CS
The SYS8V512FK is plastic 4M Static RAM Module
housed in a standard 32 pin Dual-In-Line package
organised as 512K x 8. The module is designed to
operate at low Vcc (3.3V ± 10%).
The module utilises four fast 128Kx8 SRAMs
housed in SOJ packages, double sided surface
mount techniques, buried decoder and dual board
construction to achieve a very high density module.
The module has Chip Select, Write Enable and
Output Enable control inputs; the Output Enable
pin allows faster access times than address access
during a Read Cycle.
Plastic 32 Pin 0.6" JEDEC DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
TOP VIEW
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
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