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参数资料
| 型号： | T436416D-6C |
| 厂商： | TM Technology, Inc. |
| 英文描述： | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 4米× 16 SDRAM的100万x 16Bit的X 4Banks同步DRAM |
| 文件页数： | 9/73页 |
| 文件大小： | 734K |
| 代理商： | T436416D-6C |
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TE
CH
tm
5 Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command cannot occur within a time delay of
{
t
RP
(min.)
+ burst length
}
. At full-page burst, only the read operation is performed in this command and the auto precharge
function is ignored.
T436416D
TM Technology Inc. reserves the right
P. 9
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
RCD
(min.) before the Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and
burst sequence are determined by the mode register, which is already programmed. A full-page burst will
continue until terminated (at the end of the page it will wrap to column 0 and continue).
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DIN A3
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge.
Burst Write Operation
(Burst Length = 4, CAS# Latency = 1, 2, 3)
Extra data is masked.
don't care
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from
Write command can occur on any clock cycle following the previous Write command (refer to the following
figure).
A write burst without the auto precharge function may be interrupted by a subsequent Write,
CLK
COMMAND
T0
T 1
T2
T3
T4
T5
T6
T7
T8
DIN B2
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
WRITE B
NOP
DIN A0
DIN B0
DIN B1
DQ's
DIN B3
1 Clk Interval
Write Interrupted by a Write
(Burst Length = 4, CAS# Latency = 1, 2, 3)
cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input
data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs
(refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes
will not be executed.
The Read command that interrupts a write burst without auto precharge function should be issued one
相关PDF资料 |
PDF描述 |
|---|---|
| T436416D-6CG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-6S | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-6SG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7C | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7CG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| T436416D-6CG | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-6S | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-6SG | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7C | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7CG | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
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