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| 型号： | T436416D-6CG |
| 厂商： | TM Technology, Inc. |
| 英文描述： | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| 中文描述： | 4米× 16 SDRAM的100万x 16Bit的X 4Banks同步DRAM |
| 文件页数： | 19/73页 |
| 文件大小： | 734K |
| 代理商： | T436416D-6CG |
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TE
CH
tm
T436416D
TM Technology Inc. reserves the right
P. 19
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
6. A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
7. Transition times are measured between V
IH
and V
IL
. Transition(rise and fall) of input signals are in a fixed slope (1
ns).
3.3V
1.2k
870
30pF
Output
1.4V
50
Output
30pF
50
Z0=
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
8. t
HZ
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, ( t
R
/ 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time t
T
( t
R
& t
F
) = 1 ns
If t
R
or t
F
is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be
added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V
DD
and V
DDQ
(simultaneously) when all input signals are held "NOP" state and both
CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200us minimum is required. Then, it is recommended that DQM is held "HIGH"
(V
DD
levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
相关PDF资料 |
PDF描述 |
|---|---|
| T436416D-6S | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-6SG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7C | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7CG | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7S | 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| T436416D-6S | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-6SG | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7C | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7CG | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
| T436416D-7S | 制造商:TMT 制造商全称:TMT 功能描述:4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM |
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