T5750
Preliminary Information
Rev. A2, 11-Apr-01
3 (10)
CLK
PA_ENABLE
ANT2
ANT1
ENABLE
GND
VS
XTAL
1
2
3
4
5
6
7
8
VCO
LF
CP
PFD
f
64
XTO
PLL
PA
f
4
T5750
Power up / down
Figure 3. Block diagram
General Description
This fully integrated PLL transmitter allows particularly
simple, low cost RF miniature transmitters to be as-
sembled. The VCO is locked to 64
fXTAL hence a
13.5672 MHz crystal is needed for a 868.3 MHz transmit-
ter and a 14.2969 MHz crystal for a 915 MHz transmitter.
All other PLL and VCO peripheral elements are inte-
grated.
The XTO is a series resonance oscillator so that only one
capacitor together with a crystal connected in series to
GND are needed as external elements.
The crystal oscillator together with the PLL needs
typ.<1ms until the PLL is locked and the CLK output is
stable. A wait time of
w 4 ms must be used until the CLK
is used for the uC and the PA is switched on.
The power amplifier is an open collector output deliver-
ing a current pulse which is nearly independent to the load
impedance. The delivered output power is hence control-
lable via the connected load impedance.
This output configuration enables a simple matching to
any kind of antenna or to 50
W. A high power efficiency
of
h=Pout/(IS,PA VS ) of 24% for the power amplifier @
868.3 MHz results when an optimised load impedance of
ZLoad= (166 + j226)
W is used at 3 V supply voltage.
Functional Description
If ENABLE = L and the PA_ENABLE=L the circuit is in
standby mode consuming only a very small amount of
current, so that a lithium cell used as power supply can
work for several years.
With ENABLE=H the XTO, PLL and the CLK driver are
switched on. If PA_ENABLE stay L only the PLL and the
XTO is running and the CLK signal is delivered to the
mC.
The VCO locks to 64 times the XTO frequency.
With ENABLE=H and PA_ENABLE=H the PLL, XTO,
CLK driver and the power amplifier are on. With PA_EN-
ABLE the power amplifier can be switched on an off,
which is used to perform the ASK modulation.
ASK Transmission
The T5750 is activated by ENABLE = H. PA_ENABLE
must remain L for t
w 4 ms, then the CLK signal is taken
to clock the
mC and output power can be modulated by