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参数资料
| 型号： | T6B70BFG |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封装： | 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOP-16 |
| 文件页数： | 7/20页 |
| 文件大小： | 405K |
| 代理商： | T6B70BFG |
T6B70BFG
2006-07-14
15
Toshiba CMOS SOP Embossed Taping - Common Specifications
1.
Applicable Scope
This specification defines the embossed taping package specifications and related items for Toshiba flat
package CMOS ICs. As a rule, these taping specifications comply with JEITA (RC-1009B) and EIA (EIA481).
2.
Specifications
2.1
Tape Form and Dimensions
Package
JEITA Tape Standard
300 mm 14, 16 pin (JEITA Type II)
TE1612
300 mm 20 pin (JEITA Type II)
TE2412
Unit: mm
A
B
W
F
E
P1
P2
P0
φD0
t
T1
φD1
14, 16
pin type
8.5
± 0.2
10.8
± 0.2
16.0
± 0.3
7.5
± 0.1
1.75
± 0.1
12.0
± 0.1
2.0
± 0.1
4.0
± 0.1
1.5
+ 0.1
0
0.3
± 0.1
2.1
± 0.2
1.65
± 0.1
20
pin type
8.3
± 0.2
13.2
± 0.2
24.0
± 0.3
11.5
± 0.1
1.75
± 0.1
12.0
± 0.1
2.0
± 0.1
4.0
± 0.1
1.5
+ 0.1
0
0.3
± 0.1
2.2
± 0.2
2.0
± 0.2
Note 1: The tape surface resistance shall be 10
6 Ω/cm or less.
Note 2: The accumulated error tolerance for the feed hole pitch (P0) shall be
≤ ± 0.2 mm per 10 pitches.
Y
X
Y
P1
P2 P0
φD0
φD1
F
W
E
Direction of feed
B
t
T1
Section view Y-Y
A
Section view X-X
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