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参数资料
| 型号： | T6N71B |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 6/19页 |
| 文件大小： | 241K |
| 代理商： | T6N71B |
T6N71B
2003-08-07
14
5. Pin Assignment
5.1
Outline of Functions
Pin Name
Input/
output
Function
PSK_TXD0/1
Output
Antenna output pin (carrier and data output pin)
MOD_OUT
Output
Sub carrier output pin
Transmit
cir
cuit
VDD_TX, GND_TX
Transmit-circuit-only power supply pins
AMP0_IN0
Input
PSK receive wave amp (AMP0) input pin
AMP0_IN1
Input
PSK receive wave amp (AMP0) input pin
AMP0_OUT
Output
PSK receive wave amp (AMP0) output pin
AMP1_IN0
Input
PSK receive wave amp (AMP1) input pin
AMP1_IN1
Input
PSK receive wave amp (AMP1) input pin
BYPASS
Amp stabilizing capacitor connecting pin
Receive
cir
cuit
VDD_A, GND_A
Receive-circuit-only power supply pins
/RST
Input
System reset input pin
PSK_RXD
Input/
output
Receive carrier input/output pin (pull-up resistor connected at input)
SYNC_IN
Input
Transmit sync signal input pin
SYNC_OUT
Output
Transmit sync signal output pin
SI
Input
CPU interface serial input (sync/start-stop sync) pin
SO
Output
CPU interface serial output (sync/start-stop sync) pin
/SCK
Output
Serial clock (sync) /SIO clock (start-stop sync) pin
CONT
Input
Control pin (when L, register setting mode)
PC_RXD
Input
External interface receive input (start-stop sync) pin
PC_TXD
Output
External interface trsnsmit output (start-stop sync) pin
PC_SCK
Input
External interface clock generation baud generator input pin
SYN_ASYN
Input
CPU interface clock sync/start-stop sync switching pin
BAUD_SEL0/1
Input
Initial transfer rate select pin
PLL_LOCK
Output
PLL lock detection pin
SIO_ERR
Output
RFID receive data (clock sync) error detection pin
Logic
circuit
VDD_D0~D01, GND_D0~D02,
VDD_OSC, GND_OSC
Logic circuit and oscillator power supply pins
XI, XO
Oscillation circuit. Crystal oscillator, ceramic oscillator, capacitor, and
resistor are externally connected.
OSC_OUT
Output
Oscillation frequency output pin
/XE
Input
Oscillator and receive circuit enable pin. When set to L, oscillation starts.
/BUP
Input
Oscillator Beta Up mode enable pin. When set to L, Beta Up mode.
VDET0/1
Output
Pin for detection signal output from power voltage detection circuit
Others
/VDETEN
Input
Power voltage detection circuit enable pin. When set to L, enables the
detector.
Total: 44 pins (4 NC pins are not included.)
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