参数资料
型号: T89C51AC2-SLSIM
厂商: Atmel
文件页数: 53/121页
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44PLCC
标准包装: 27
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
37
A/T89C51AC2
4127H–8051–02/08
Overview of FM0
Operations
The CPU interfaces to the Flash memory through the FCON register and AUXR1
register.
These registers are used to:
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the Flash memory (busy/not busy)
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 24. A MOVC instruction is then used for reading these spaces.
Table 24. FM0 Blocks Select Bits
Launching Programming
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 25 summarizes the memory
spaces to program according to FMOD1:0 bits.
FMOD1
FMOD0
FM0 Adressable space
0
User (0000h-7FFFh)
0
1
Extra Row(FF80h-FFFFh)
1
0
Hardware Security Byte (0000h)
1
Reserved
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