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参数资料
| 型号： | T90FJR-5VTX |
| 厂商： | ATMEL CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封装： | GREEN, PLASTIC, VQFP-128 |
| 文件页数： | 7/42页 |
| 文件大小： | 358K |
| 代理商： | T90FJR-5VTX |
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15
4152B–ASSP–09/05
A/T90FJR
6.1
Hot Plug and Bypass
As a module can be inserted or removed at any time, in order not to break the daisy chain, the
CIMaX handles one MPEG transport stream bypass for each module. This bypass is enabled
as long as a valid DVB CI module is not recognized to be inserted and activated in the corre-
sponding slot or automatically as soon as the module is removed from a slot. The disabling of
the bypass is controlled by the TSOEN bit in each Module Control Register. The bypass can be
switched at any time, regardless of the MPEG stream synchronization.
6.1.1
TS swap (SCM Patent Pending)
With standard conditional access modules, the order in which the transport stream passes
through has no influence. However, in some particular cases, it can be useful to choose which
module is first in the TS daisy chain. The TSWAP bit in the Destination Select Register when set,
virtually swaps the two modules so that the MPEG stream passes first in the B module and then
in the A module.
6.1.2
TS / Addresses input signals
The MPEG input stream pins on the module are shared with the high order addresses specified
by the PC Card standard. When a module is inserted, before initialization, all these pins are
forced to logical 0 state. If a memory module is recognized, the high order addresses A[25..15]
can be applied to the module by setting the HAD bit in the Module Control Register. If a DVB
module is recognized, the MPEG stream is applied to the module by setting the TSIEN bit in the
Module Control Register. Those two bits cannot be set at the same time and are reset when the
module is extracted
When HAD is set, the maximum propagation delay between A[25..15] inputs and TS outputs to
the modules is 25 ns with a load of 50 pF on the outputs.
The TSOEN bit (TS bypass control bit) can only be set when TSIEN has previously been set.
Resetting TSIEN also resets TSOEN.
6.1.3
Invert mask
Some modules can output an MPEG stream with inverted bits in the MPEG data bus. The
CIMaX is able to re-invert those bits to restore the correct data on the bus. This is achieved by
setting the appropriate bits in the Invert Mask Register.
2:1 mux
TS in
TS out
Module #i
Control
2:1 mux
TS in
TS out
Module #i
Control
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