参数资料
型号: TA1370FG
元件分类: 信号分离
英文描述: SYNC SEPARATOR IC, PDSO30
封装: 0.375 INCH, 1 MM PITCH, PLASTIC, SSOP-30
文件页数: 7/42页
文件大小: 902K
代理商: TA1370FG
TA1370FG
2005-09-05
15
Read Mode
POR (Power on reset)
(0): Status read (at second data read and subsequent)
(1): Power on (at first data read)
HD-IN (Input signal self-check result)
Detects HD or H-SYNC input signal selected by INPUT SW.
(0): No signal input (1): Signal input
V FREQ DET (Vertical frequency of SYNC or VD input selected by FREQ DET SW)
(0000000)(0001100): No-VD
(0001101) : Vicinity of 162 Hz
(1111111) : Vicinity of 17 Hz
How to calculate vertical frequency (X):
Convert V-FREQ DET read data into decimal and define the resulting value as Y.
Where H-FREQUENCY is 31.5 kHz, Z = 476.2 s
Where H-FREQUENCY is 28.125 kHz/33.75 kHz/45 kHz, Z = 474.1 s
Vertical frequency (X) = 1 ÷ (Y × Z) [Hz]
Error of Y is +1, 0. If vertical frequency is 162 Hz or more, the frequency cannot be accurately
measured. Time constant used to separate V.SYNC from integrated C.SYNC is 9 s (error: ±1 s).
H FREQ DET (Horizontal frequency of SYNC or HD input selected by FREQ DET SW)
(0000000): No signal input (1111111): 53 kHz or more
How to calculate horizontal frequency (X):
X, Y, and Z are defined same as for V FREQ.
Horizontal frequency (X) = Y ÷ (5 × Z) [kHz]
Error of Y is +1, 0. If horizontal frequency is 53 kHz or more, the frequency cannot be accurately
measured. When V-SYNC or VD is not input, horizontal frequency cannot be measured, resulting in
data = (0000000).
Note 1: The start trigger for frequency counting is the internal reset-pulse made from ACK of 2nd byte in BUS
read mode. The counting period is between the first V-sync (VD) and the second V-sync (VD) after the
trigger.
The counted data will have +1 or 0 error according to the read timing.
To assume stable data reading;
1. Set BUS reading interval more than 3 V.
2. Don’t use the first data because it is unsettled.
are recommended.
Note 2: Ignore data (H FREQUENCY DET, V FREQUENCY DET) = (0000001, 0001101). This data is obtained
when the pin voltage of SYNC-IN pin is higher than sync separation level and when any signal is not
inputted into SYNC-IN pin.
Decision algorithm (detection range, detection times and so on) should be determined under
consideration of Note 1, Note 2 and the other factors such as signal strength, existence of ghost signal,
H-AFC stability, I2C BUS data transmission and so on via prototype TV set evaluation.
Read Timing
V-SYNC or VD
More than 3 V
Counting period 1
(to Data 1)
Counting period 2
(to Data 2)
Start trigger 1
Data 1 and
Start trigger 2
Data 2 and
Start trigger 3
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