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参数资料
| 型号： | TA1384FNG |
| 元件分类： | 调谐器 |
| 英文描述： | 2-BAND, VIDEO TUNER, PDSO24 |
| 封装： | 0.300 INCH, 0.65 MM PITCH, LEAD FREE, PLASTIC, SSOP-24 |
| 文件页数： | 4/22页 |
| 文件大小： | 302K |
| 代理商： | TA1384FNG |
TA1384FNG
2004/11/24
12
BYTE 4
Byte 4 is a control byte used to set the different functions. Bit 2 (CP) and controls the output current of the charge-pump
circuit. When bit 2 is set to [0], the output current is set to +55
A; when it is set to [1] , it is +250 A.
Bit 3 (T2), bit 4 (T1), and bit 5 (T0) are used to set the phase comparator reference signal output and counter divider
output in test mode. (For details of test mode, see the test mode setting table.)
Bit 6 (Rsa) and bit 7 (Rsb) are used to set the crystal reference frequency divider ratio. (For details of the crystal
reference frequency divider ratio, see the table for crystal reference frequency divider ratios.)
Bit 8 (OS) is used to set the charge-pump driver amplifier output setting. When bit 8 is set to [0], the output is ON (the
normal setting used); when it is set to [1], the output is OFF (charge pump is sink mode).
BYTE 5
Byte 5 is used to set the test mode and control the output ports (Band 1 ~ Band 4).
When an output port is set to [0], it is OFF; when it is set to [1], it is ON.
Bandswitch setting is also used to switch between the VHF and UHF bands.
·
When the bandswitch data for either B1 or B2 is [1], VHF mode is effective.
·
When the bandswitch data for both B1 and B2 is [0], UHF mode is effective.
Set the following maximum values for currents to the bandswitch driver. Ensure also that the total band current is
within 17 mA when two bands are operating at the same time.
·
Band 1 (pin 4) output current:
7 mA (maximum)
·
Band 2 (pin 5) output current: 10 mA (maximum)
·
Band 3 (pin 6) output current:
3 mA (maximum)
·
Band 4 (pin 7) output current:
7 mA (maximum)
B) READ MODE (Status Request)
When Read Mode is set, power-on reset operation status and phase comparator lock detector output status are output to
the master device.
Bit 1 (POR) indicates the power-on reset operation status. When the power supply of Vcc stops, this bit is set to [1]. The
conditions for reset to [0] are that voltage supplied to Vcc is 3V or higher, that transmission is requested in READ MODE,
and that the status is output. (When Vcc is turned on, bit 1 is also set to [1].)
Bit 2 (FL) indicates the phase comparator lock status. When this is locked, [1] is output; when it is unlocked, [0] is
output.
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