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| 型号： | TA8007S |
| 元件分类： | 固定正电压单路输出标准稳压器 |
| 英文描述： | 5 V FIXED POSITIVE REGULATOR, PSIP9 |
| 封装： | 2.54 MM PITCH, PLASTIC, SIP-9 |
| 文件页数： | 2/9页 |
| 文件大小： | 364K |
| 代理商： | TA8007S |
10
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
7.
AVR CPU core
7.1
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor-
rect program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
7.2
Architectural overview
Figure 7-1.
Block diagram of the AVR architecture.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper-
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct
Addressing
Indirect
Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
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