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| 型号： | TAS3204PAG |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 18/76页 |
| 文件大小： | 1224K |
| 代理商： | TAS3204PAG |
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www.ti.com
SLES197C – APRIL 2007 – REVISED MARCH 2011
8
I
2C Control Interface
The TAS3204 also two I2C interfaces that is compatible with the I2C bus protocol. The Master I2C supports
375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes). The
master I2C interface is used to load program and data from an external I2C EEPROM. The slave I2C
interface supports both 100 kbps and 400 kbps data transfer rates for multiply 4 byte write and read
operations (maximum 20 bytes). The slave I2C interface is used to program the registers of the device or
to read the device status registers. Additionally, the slave I2C can be used to replace the information
loaded by the I2C master interface.
8.1
General I
2C Operations
The I2C bus employs two signals, SDA (serial data) and SCL (serial clock), to communicate between
integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and
data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition,
each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each
transfer operation begins with the master device driving a start condition on the bus and ends with the
master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA)
while the clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA
indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur
within the low time of the clock period. The master generates the 7-bit slave address and the read/write
(R/W) bit to open communication with another device and then waits for an acknowledge condition. The
slave holds SDA LOW during acknowledge clock period to indicate an acknowledgement. When this
occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit
slave address plus R/W bit (one byte). All compatible devices share the same signals via a bidirectional
bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals
to set the HIGH level for the bus.
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. Figure 8-1 shows the
TAS3204 read and write operation sequences.
transaction to give the TAS3204 the subaddress to be used in the read transaction that follows. This
subaddress assignment write transaction is then followed by the read transaction. For write transactions,
the subaddress is supplied in the first byte of data written, and this byte is followed by the data to be
written. For I2C write transactions, the subaddress must always be included in the data written. There
cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If
a subaddress-assignment-only write transaction is followed by a second write transaction supplying the
data, erroneous behavior results. The first byte in the second write transaction is interpreted by the
TAS3204 as another subaddress replacing the one previously written.
Copyright 2007–2011, Texas Instruments Incorporated
25
I2C Control Interface
Product Folder Link(s): TAS3204
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