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参数资料
| 型号： | TAS5000PFB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | GREEN, TQFP-48 |
| 文件页数： | 3/25页 |
| 文件大小： | 108K |
| 代理商： | TAS5000PFB |
2–1
2 Functional Description
2.1
Serial Audio Port
The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and
a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1 kHz, 48 kHz, 88.2 kHz,
or 96 kHz) stereo. See section 2.8 for Serial Interface Formats.
2.2
System Clocks – Master Mode and Slave Mode
The TAS5000 allows multiple system clocking schemes. In this document, master mode indicates that the TAS5000
provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256Fs MCLK_OUT,
64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode indicates
that a system master other than the TAS5000 provides system clocks (LRCLK, SCLK, and MCLK_IN) to the TAS5000
(M_S = 0). The TAS5000 operates with LRCLK and SCLK synchronized to MCLK. TAS5000 does not require any
specific phase relationship between LRCLK and MCLK, but there must be synchronization. If the synchronization
between MCLK and LRCLK changes more than 10 MCLK periods during one sample period (LRCLK), the TAS5000
will initiate an internal reset. In the slave mode MCLK_OUT is driven low. Table 2–1 shows all the possible master
and slave modes.
2.3
Oscillator/Sampling Frequency
The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which should
be either 11.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). Twice the normal sampling frequency can be
selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs = 96 kHz. In the double-speed slave
mode (DBSPD = 1, M_S = 0), the external clock input is either 22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz
(Fs = 96 kHz). Table 2–1 explains the proper clock selection.
2.4
Phase Locked Loop (PLL)/Clock Generation
A low jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as
PLL_FLT_RET and PLL_FLT_OUT. See Figure 5–1 for a suggested external loop filter. If the PLL loses lock, the error
status pin (ERR) will go low. Note that ERR can go low for other conditions as well. See section 2.7.7 Error Status
Reporting.
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