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参数资料
| 型号： | TAS5012PFBG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | PLASTIC, TQFP-48 |
| 文件页数： | 13/18页 |
| 文件大小： | 245K |
| 代理商： | TAS5012PFBG4 |
TAS5012
SLES006A SEPTEMBER 2001 REVISED DECEMBER 2001
4
www.ti.com
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD1
48
I
Analog supply for oscillator
AVDD2
2
I
Analog supply for PLL
AVSS1
44
I
Analog ground for oscillator
AVSS2
5
I
Analog ground for PLL
DBSPD
39
I
Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_EN
43
I
De-emphasis enable, active high
DEM_SEL
42
I
De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz)
DVDD1
12, 14
I
Digital voltage supply for logic
DVDD2
31
I
Digital voltage supply for PWM reclocking
DVDD3_L
36
I
Digital voltage supply for PWM output (left)
DVDD3_R
25
I
Digital voltage supply for PWM output (right)
DVSS1
13, 15
I
Digital ground for logic
DVSS2
30
I
Digital ground for PWM reclocking
DVSS3_L
37
I
Digital ground for PWM output (left)
DVSS3_R
24
I
Digital ground for PWM output (right)
FTEST
41
I
Tied to DVSS1 for normal operation
LRCLK
18
I/O
Left/right clock (input when M_S = 0; output when M_S = 1)
MCLK_IN
1
I
MCLK input
MCLK_OUT
16
O
Buffered system clock output if M_S = 1; otherwise set to 0
MOD0
22
I
Serial interface selection pin, bit 0
MOD1
21
I
Serial interface selection pin, bit 1
MOD2
20
I
Serial interface selection pin, bit 2 (MSB)
M_S
10
I
Master/slave, master=1, slave=0
MUTE
38
I
Muted signal = 0, normal mode = 1
NC
6, 11
No connection
OSC_CAP
45
I
Oscillator cap return
PDN
8
I
Power down, active low
PLL_FLT_OUT
3
O
Output terminal for external PLL filter
PLL_FLT_RET
4
I
Return for external PLL filter
PWM_AM_L
34
O
PWM left output A (differential )
PWM_AM_R
28
O
PWM right output A (differential )
PWM_AP_L
35
O
PWM left output A (differential +)
PWM_AP_R
29
O
PWM right output A (differential +)
PWM_BM_L
33
O
PWM left output B (differential )
PWM_BM_R
27
O
PWM right output B (differential )
PWM_BP_L
32
O
PWM left output B (differential +)
PWM_BP_R
26
O
PWM right output B (differential +)
RESET
7
I
Reset (active low)
SCLK
17
I/O
Shift clock (input when M_S = 0, output when M_S = 1)
SDIN
19
I
Stereo serial audio data input
STEST
40
I
Tied to DVSS1 for normal operation
VALID_L
23
O
PWM left outputs valid (active high)
VALID_R
9
O
PWM right outputs valid (active high)
XTL_IN
47
I
Crystal or clock input (MCLK input)
XTL_OUT
46
O
Crystal output (not for external usage). NC when XTL_IN is MCLK input
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