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参数资料
| 型号： | TAS5026IPAGG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 14/50页 |
| 文件大小： | 717K |
| 代理商： | TAS5026IPAGG4 |
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Architecture Overview
16
SLES041B—November 2002
TAS5026
2.2.2 Power Down—PDN
The TAS5026 can be placed into the power-down mode by holding the PDN terminal low. When power-down
mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation
(there is no ramp down). The valid 1–6 outputs are immediately asserted low and the PWM outputs are placed
in the hard mute state. PDN initiates device power down without clock inputs. As long as the PDN terminal
is held low—the device is in the power-down (hard mute) state.
During power down, all I2C and serial data bus operations are ignored. Table 2–8 shows the device output
signals while PDN is active.
Table 2–8. Device Outputs During Power Down
SIGNAL
MODE
SIGNAL STATE
Valid 1–Valid 6
All
Low
PWM P-outputs
All
Low
PWM M-outputs
All
Low
MCLKOUT
All
Low
SCLK
Master
Low
SCLK
Slave
Signal input
LRCLK
Master
Low
LRCLK
Slave
Signal input
SDA
All
Signal input
CLIP
All
High
To place the device in total power-down mode, both RESET and power-down modes must be enabled. Prior
to bringing PDN high, RESET must be brought low for a minimum of 50 ns.
Because PDN is an asynchronous control signal, small clicks and pops can be produced during the application
(the leading edge) of this control. However, when PDN is released, the transition from the hard mute state back
to normal operation is performed synchronously using a quiet sequence.
If a completely quiet reset sequence is desired, MUTE should be applied before applying PDN.
2.2.2.1
Recovery Time Options
To support the requirements of various system configurations, the TAS5026 can come up to the normal state
after either a long (100 ms) or a short (5 ms) delay.
1.
In the first case, a slow system (95 ms to 100 ms) start-up occurs at the end of the power-down sequence
when:
RESET is high for at least 16 MCLK_IN periods before PDN goes high.
2.
Otherwise a fast (4 ms to 5 ms) start up occurs.
NOTE: If MCLK_IN is not active when both of these signals are released high, then a a fast
(4 ms to 5 ms) start up occurs once MCLK_IN becomes active.
2.2.3 Status Registers
The TAS5026 provides device identification and operational status information that is accessible through the
serial control interface status registers that provide general device information.
Device ID—The TAS5026 provides a device identification code that is accessible through the serial control
interface
Volume Update is in Progress—Whenever a volume change is in progress, this status bit is high.
No Internal Errors (All Valid Signals are High)—When there are no internal errors in the TAS5026 and all
outputs are valid, this status bit is high.
LRCLK Error—When there are the MCLK_IN rate changes more than
±10 MCLK_IN cycles from the correct
number of cycles (128 or 256) per LRCLK cycle
MCLK_IN Error—When the MCLK_IN frequency changes such that it is out of synchronization with internal
PLL generated clock
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| TAS5026IPAGR | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026IPAGRG4 | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026PAG | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026PAGG4 | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
| TAS5026PAGR | 功能描述:多媒体杂项 Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 类型: 通道数量: 转换速率:540 Mbps 分辨率: 封装 / 箱体:SOIC-16 封装:Tube |
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