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参数资料
| 型号： | TAS5036APFCG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | GREEN, PLASTIC, TQFP-80 |
| 文件页数： | 6/64页 |
| 文件大小： | 950K |
| 代理商： | TAS5036APFCG4 |
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Architecture Overview
8
SLES061B—November 2002—Revised January 2004
TAS5036A
If the master clock input can encounter high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET should be applied during this time. There are two recommended control
procedures for this case, depending upon whether the DBSPD terminal or the serial control interface is used.
These control sequences are shown in Section 4.
Table 21. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
DBSPD TERMINAL OR
CONTROL REGISTER BIT
MODE
SPEED SELECTION
0
Master or slave
Normal speed
0
1
Master or slave
Double speed
1
0
Master or slave
Quad speed
0
Slave
Quad speed if MCLK_IN = 128Fs
1
Master or slave
Error
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
The transition to master mode occurs following a RESET when M_S terminal has a logic high applied.
The transition to slave mode occurs following a RESET when M_S terminal has a logic low applied.
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5036A provides the master clock, SCLK, and LRCLK to the rest
of the system. In the master mode, the TAS5036A outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5036A device generates these clocks plus its internal clocks from the internal phase-locked loop
(PLL). The reference clock for the PLL can be provided by either an external clock source (attached to
XTAL_IN) or a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached
to MCLK_IN is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the
data sample rate and the SCLK frequency of 48 times the data sample rate is not supported in the master
mode. The LRCLK frequency is the data sample rate.
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相关代理商/技术参数 |
参数描述 |
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| TAS5036APFCR | 功能描述:音频放大器 Digital Audio PWM Processor RoHS:否 制造商:STMicroelectronics 产品:General Purpose Audio Amplifiers 输出类型:Digital 输出功率: THD + 噪声: 工作电源电压:3.3 V 电源电流: 最大功率耗散: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:TQFP-64 封装:Reel |
| TAS5036APFCRG4 | 功能描述:音频放大器 Digital Audio PWM Processor RoHS:否 制造商:STMicroelectronics 产品:General Purpose Audio Amplifiers 输出类型:Digital 输出功率: THD + 噪声: 工作电源电压:3.3 V 电源电流: 最大功率耗散: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:TQFP-64 封装:Reel |
| TAS5036B | 制造商:TI 制造商全称:Texas Instruments 功能描述:Six Channel Digital Audio PWM Precessor |
| TAS5036B_06 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Six Channel Digital Audio PWM Processor |
| TAS5036BPFC | 功能描述:音频 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
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