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| 型号： | TAS5036IPFCG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | GREEN, PLASTIC, TQFP-80 |
| 文件页数： | 3/49页 |
| 文件大小： | 716K |
| 代理商： | TAS5036IPFCG4 |
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Architecture Overview
6
SLES044B—November 2002
TAS5036
2
Architecture Overview
The TAS5036 is composed of six functional elements:
Clock, PLL, and serial data interface (IIS)
Reset/power down circuitry
Serial control interface (IIC)
Signal processing unit
Pulse width modulator (PWM)
Power supply
2.1
Clock and Serial Data Interface
The TAS5036 clock and serial data interface contains an input serial data slave and the clock master/ slave
interface.
The serial data slave interface receives information from a digital source such as a DSP, S/PDIF receiver,
analog-to-digital converter (ADC), digital audio processor (DAP) such as the TAS3103, or other serial bus
master at sample rates of for sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,176.4 kHz, and 192
kHz. The serial data interface has three serial data inputs that can accept up to six channels of data. The serial
data interfaces support left justified and right justified for 16-, 20-, and 24-bits. In addition, the serial data
interfaces support the DSP protocol for 16 bits and the I2S protocal for 24 bits. The received data is data
passed to the TAS5036 signal-processing unit.
The TAS5036 can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),
and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The
TAS5036 is a clock master when it generates these clocks and is a clock slave when it receives these clocks.
The TAS5036 is a synchronous design that relies upon master clock to provide a reference clock for all of the
device operations. When operating as a slave, this reference clock is MCLK_IN. When operating as a master,
the reference clock is either TTL clock input to XTAL_IN or a crystal attached across XTAL_IN and XTAL_OUT.
If the master clock stops, the TAS5036 will perform a clock error recovery sequence. The clock error recovery
sequence temporarily suspends processing, places the PWM outputs in a hard mute (PWM P outputs are low;
PWM M outputs are high, and all VALID signals are low), resets all internal processes, sets the volumes to
mute, and suspends all I2C operations.
When the master clock is resumed, the TAS5036 exits the clock error recovery sequence by performing a
4.3-ms partial re–initialization, noiselessly restarting the PWM output, and ramping the volume up to the level
specified in the volume control registers. The volume update is performed over a 43 ms. interval. The TAS5036
will preserve all control register settings that were set prior to the clock interruption.
Quad–speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. Quad–speed mode is auto
detected supported in slave mode and invoked by control in master mode in slave mode. If the device is not
in double speed mode, quad–speed mode is automatically detected when MCLK_IN is 128Fs. In master
mode, the PWM is placed in quad–speed mode by setting the quad–speed bit in the system control register
through the serial control interface.
The clock and serial data interface has two control parameters: data sample rate and clock master or slave.
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
The sampling rate is selected through a pin (DBSPD) or the serial control register 0 (X02). When a sample
rate is selected, the system automatically performs an error recovery sequence and switches to the new
sampling rate. As shown in subsequent sections, the sample rate control sets the frequencies of the SCLK
and LRCLK in clock slave mode and the output frequencies of SCLK and LRCLK in clock master mode.
The reference clock for the PLL can be provided by either an external clock source (attached to XTAL_IN) or
a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached to MCLK_IN
is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample
rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK
frequency is the data sample rate.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TAS5036IPFCR | 功能描述:音频 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS5036IPFCRG4 | 功能描述:音频 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| TAS5036PFC | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5036PFCR | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR |
| TAS5066 | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIX-CHANNEL Digital Audio PWM Processor |
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